DE2之7-segment displays

　　以前课题用的是友晶的DE2-70，现在重拾FPGA，选了一款性价比高的DE2。恰逢闲来无事，于是尝试将各个Verilog模块翻译成VHDL，半算回顾以前的知识，半算练习VHDL。

Verilog 01

 module SEG7_LUT    (    oSEG,iDIG    );
 input    [:]    iDIG;
 output    [:]    oSEG;
 reg        [:]    oSEG;
 
 always @(iDIG)
 begin
     case(iDIG)
     'h1: oSEG = 7'b1111001;    // ---t----
     'h2: oSEG = 7'b0100100;     // |      |
     'h3: oSEG = 7'b0110000;     // lt     rt
     'h4: oSEG = 7'b0011001;     // |      |
     'h5: oSEG = 7'b0010010;     // ---m----
     'h6: oSEG = 7'b0000010;     // |      |
     'h7: oSEG = 7'b1111000;     // lb     rb
     'h8: oSEG = 7'b0000000;     // |      |
     'h9: oSEG = 7'b0011000;     // ---b----
     'ha: oSEG = 7'b0001000;
     'hb: oSEG = 7'b0000011;
     'hc: oSEG = 7'b1000110;
     'hd: oSEG = 7'b0100001;
     'he: oSEG = 7'b0000110;
     'hf: oSEG = 7'b0001110;
     'h0: oSEG = 7'b1000000;
     endcase
 end
 
 endmodule

VHDL 01

 library IEEE;
 use ieee.std_logic_1164.all;
 
 4 --! 7-segment displays
 entity SEG7_LUT is
 port
 (
   iDIG : in std_logic_vector( downto );
   oSEG : out std_logic_vector ( downto )
 );
 end SEG7_LUT;
 
 architecture fpga of SEG7_LUT is
 
 begin
 
 pseg: process(iDIG)
 begin
   case iDIG is
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
     when "" =>
       oSEG <= "";
 
     end case;
 
 end process;
 
 end fpga;

Verilog 02

 module SEG7_LUT_8 (oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
 input    [:]    iDIG;
 output    [:]    oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
 
 SEG7_LUT    u0    (    oSEG0,iDIG[:]        );
 SEG7_LUT    u1    (    oSEG1,iDIG[:]        );
 SEG7_LUT    u2    (    oSEG2,iDIG[:]    );
 SEG7_LUT    u3    (    oSEG3,iDIG[:]    );
 SEG7_LUT    u4    (    oSEG4,iDIG[:]    );
 SEG7_LUT    u5    (    oSEG5,iDIG[:]    );
 SEG7_LUT    u6    (    oSEG6,iDIG[:]    );
 SEG7_LUT    u7    (    oSEG7,iDIG[:]    );
 
 endmodule

VHDL 02

 library IEEE;
 use ieee.std_logic_1164.all;
 
 4 --! oSEG0 ~ oSEG7
 entity SEG7_LUT_8 is
 port
 (
   iDIG  : in std_logic_vector( downto );
   oSEG0 : out std_logic_vector ( downto );
   oSEG1 : out std_logic_vector ( downto );
   oSEG2 : out std_logic_vector ( downto );
   oSEG3 : out std_logic_vector ( downto );
   oSEG4 : out std_logic_vector ( downto );
   oSEG5 : out std_logic_vector ( downto );
   oSEG6 : out std_logic_vector ( downto );
   oSEG7 : out std_logic_vector ( downto )
 );
 end SEG7_LUT_8;
 
 --! architecture
 architecture fpga of SEG7_LUT_8 is
 
 begin
 
 U0 : entity SEG7_LUT port map(oSEG => oSEG0,iDIG => iDIG( downto ));
 U1 : entity SEG7_LUT port map(oSEG => oSEG1,iDIG => iDIG( downto ));
 U2 : entity SEG7_LUT port map(oSEG => oSEG2,iDIG => iDIG( downto ));
 U3 : entity SEG7_LUT port map(oSEG => oSEG3,iDIG => iDIG( downto ));
 U4 : entity SEG7_LUT port map(oSEG => oSEG4,iDIG => iDIG( downto ));
 U5 : entity SEG7_LUT port map(oSEG => oSEG5,iDIG => iDIG( downto ));
 U6 : entity SEG7_LUT port map(oSEG => oSEG6,iDIG => iDIG( downto ));
 U7 : entity SEG7_LUT port map(oSEG => oSEG7,iDIG => iDIG( downto ));
 
 end fpga;