英语文档阅读学习系列之ZYNQ-7000 All Programmable SOC Packaging and Pinout

UG865-Zynq-7000-pkg-pinout

1、Table

一个overview和其他部分的构成一个整体。

2、overview

This section describes the pinouts for the Zynq-7000 All Programmable (AP) SoC available
in 0.8 mm pitch wire bond and various 0.8 mm and 1.0 mm pitch flip-chip and fine-pitch
BGA packages.
Package inductance is minimized as a result of optimal placement and even distribution as
well as an optimal number of Power and GND pins.
Flip-chip packages (FFG, FBG, SBG, RFG) are RoHS 6 of 6 compliant, with exemption 15
where there is lead in the C4 bumps that are used to complete a viable electrical connection
between the semiconductor die and the package substrate. Flip-chip packages (FFV, FBV,
SBV) are RoHS 6 of 6 compliant without the use of exemption 15. Non-flip chip packages
(CLG) are RoHS 6 of 6 compliant. Selected packages include a Pb-only option.
All of the Zynq-7000 AP SoC devices supported in a particular package are pinout
compatible.

首先，这里的目标是zynq的封装，可以大致浏览一下。

The Zynq-7000 AP SoC contains a large number of fixed and flexible I/O. Zynq-7000 AP SoC
has a constant 128 pins dedicated to memory interfaces (DDR I/O), multiplexed peripherals
(MIO), and control. Programmable logic provides additional pins for SelectIO resources
(SIO) and multi-gigabit serial transceivers (GTP or GTX) that scale by device as well as fixed
pins for configuration and analog-to-digital conversion (XADC). SIO can be used to extend
the MIO to further leverage the fixed peripherals of the processing system (PS).
Each device is split into I/O banks to allow for flexibility in the choice of I/O standards (see
UG471, 7 Series FPGAs SelectIO Resources User Guide). The PS I/Os are described in UG585,
Zynq-7000 All Programmable SoC Technical Reference Manual. Table 1-5 provides
definitions for all pin types.
Zynq-7000 AP SoCs flip-chip assembly materials are manufactured using ultra-low alpha
(ULA) materials defined as <0.002 cph/cm 2 or materials that emit less than 0.002
alpha-particles per square centimeter per hour.

可以看到，这里主要涉及到IO的支持标准。

3、other parts

About ASCII Package Files
The ASCII files for each package include a comma-separated-values (CSV) version and a text
version optimized for a browser or text editor. Each of the files consists of the following:
• Device/Package name (Device—Package), date and time of creation
• Eight columns containing data for each pin:
°
Pin—Pin location on the package.
°
Pin Name—The name of the assigned pin.
°
Memory Byte Group—Memory byte group between 0 and 3. For more information
on the memory byte group, see UG586, 7 Series FPGAs Memory Interface Solutions
User Guide [Ref 7].
°
Bank—Bank number.
°
V CCAUX Group—Number corresponding to the V CCAUX_IO power supply for the given
pin. V CCAUX is shown for packages with only one V CCAUX group.
°
Super Logic Region—Number corresponding to the super logic region (SLR) in the
devices implemented with stacked silicon interconnect (SSI) technology.
°
I/O Type—CONFIG, HR, HP, MIO, DDR, or GTP/GTX depending on the I/O type. For
more information on the I/O type, see UG471, 7 Series FPGAs SelectIO Resources
User Guide [Ref 8].
°
No-Connect—This list of devices is used for migration between devices that have
the same package size and are not connected at that specific pin.

这里解释了一下ASCII的封装文件。

This chapter provides pinout, high-performance and high-range I/O bank, memory
groupings, and power and ground placement diagrams for each Zynq-7000 AP SoC
package/device combination.
The figures provide a top-view perspective.
The symbols for the multi-function I/O pins are represented by only one of the available pin
functions; with precedence (by functionality) in this order:
• PUDC_B
• AD0P/AD0N–AD15P/AD15N
• VRN, VRP, or VREF
• DQS, MRCC, or SRCC
For example, a pin description such as IO_L8P_SRCC_35 is represented with a SRCC symbol,
a pin description such as IO_L19N_T3_AD0P_VREF_35 is represented with a
AD0P/AD0N-AD15P/AD15N symbol, and a pin description such as
IO_L21N_T3_DQS_PUDC_B_34 is represented with a PUDC_B symbol.

这里说明了这章的主要内容是管脚的在设计模型中的标准。也就是软件中进行管脚分配出现的图的解释。