The STM32 SPI and FPGA communication

The STM32 SPI and FPGA communication

STM32 spi bus communication

SPI bus in the study, the protocol and hardware description is not to say that the four-wire, including clock, chip select, receive, send

SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; / / full-duplex
SPI_InitStructure.SPI_Mode = SPI_Mode_Master; / / master mode
SPI_InitStructure.SPI_DataSize = SPI_DataSize_16b; / / 16bit width
SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; / /  - 18MHz;  - 9MHz;  - .5MHz
SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; / / high byte first
SPI_InitStructure.SPI_CRCPolynomial = ;
SPI_Init (SPIx, & SPI_InitStructure);
SPI_Cmd (SPIx, ENABLE); 

SPI has no hardware control CS, can only be controlled by the software is by NSS the external GPIO to control.

Like my projects STM32 communication with the FPGA, the FPGA SPI In this state as a master of the STM32,

CS transmission data is low after the transmission must be pulled so that the FPGA can be judged SPI Transfer start and end state.

FPGA data transfer format is 16bit address +16 bit data for read 16bit

uint16_t spi_read (SPI_TypeDef * SPIx, uint32_t addr)
{
uint16_t value;
The uint16_t spi_nss;
uint16_t add;
uint32_t level; 

if (SPI1 == SPIx)
spi_nss = SPI1_PIN_NSS;
else if (SPI2 == SPIx)
spi_nss = SPI2_PIN_NSS; 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_TXE) == RESET);
GPIO_ResetBits (GPIOA, spi_nss);
SPI_I2S_SendData (SPIx, addr); / / 0xf014 >>  

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_TXE) == RESET);
SPI_I2S_SendData (SPIx 0x0); 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_RXNE) == RESET);
SPI_I2S_ReceiveData (SPIx); 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_TXE) == RESET);
GPIO_SetBits (GPIOA, spi_nss); 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_RXNE) == RESET);
the value = SPI_I2S_ReceiveData (SPIx); 

return value;
} 

Write function 

void spi_write (SPI_TypeDef * SPIx, uint32_t addr, uint16_t value)
{ 

The uint16_t spi_nss; 

uint32_t level; 

if (SPI1 == SPIx)
spi_nss = SPI1_PIN_NSS;
else if (SPI2 == SPIx)
spi_nss = SPI2_PIN_NSS; 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_TXE) == RESET);
GPIO_ResetBits (GPIOA, spi_nss);
SPI_I2S_SendData (SPIx, addr); 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_TXE) == RESET);
SPI_I2S_SendData (SPIx, value); 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_RXNE) == RESET);
SPI_I2S_ReceiveData (SPIx); 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_TXE) == RESET);
GPIO_SetBits (GPIOA, spi_nss); 

while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_RXNE) == RESET);
SPI_I2S_ReceiveData (SPIx);
} 

Take the write function example only so many design

because if it is the beginning of the function will be the NSS pin is pulled low, and then go Send as follows

GPIO_ResetBits (GPIOA, spi_nss); 
while (SPI_I2S_GetFlagStatus (SPIx, SPI_I2S_FLAG_TXE) == RESET); 
SPI_I2S_SendData (SPIx, addr);

This CS low after a period of time (the time there are about 16 clock cycles),

only CLK, this delay will reduce the transmission efficiency of the SPI

That way before CS Euphrates will soon have clk clock out

The reason why I wrote twice read it twice instead of reading a written also taking into account the efficiency problem

If you write once read it again to see a relatively large gap between each data of the waveform is not clk,

that will have to wait a period of time, then transmit a data require a relatively high speed The device is not allowed

It is worth noting that:

If the SPI master mode, the GPIO is set to 
NSS is GPIO_Mode_Out_PP 
CLK is GPIO_Mode_AF_PP 
MOSI is GPIO_Mode_AF_PP 
MISO is GPIO_Mode_IN_FLOATING

If the SPI Slave mode, the GPIO is set to 
NSS is GPIO_Mode_Out_PP 
CLK is GPIO_Mode_IN_FLOATING 
MOSI is GPIO_Mode_IN_FLOATING 
MISO is GPIO_Mode_AF_PP