异步FIFO的verilog实现与简单验证（调试成功）

最近在写一个异步FIFO的时候，从网上找了许多资料，文章都写的相当不错，只是附在后面的代码都多多少少有些小错误。

于是自己写了一个调试成功的代码，放上来供大家参考。

非原创 原理参考下面：

原文 https://www.cnblogs.com/SYoong/p/6110328.html

上代码：

 module Asyn_FIFO_tb;

     parameter WIDTH = ;

     reg clk_wr;
     reg clk_rd;
     reg rst_n_rd;
     reg rst_n_wr;

     reg  [WIDTH-:] data_wr;
     reg  wr_en;
     wire wr_full;

     wire [WIDTH-:] data_rd;
     reg  rd_en;
     wire rd_empty;

     Asyn_FIFO fifo_inst(
     .clk_wr(clk_wr),
     .rst_n_rd(rst_n_rd),
     .rst_n_wr(rst_n_wr),
     .wr_en(wr_en),
     .data_wr(data_wr),
     .clk_rd(clk_rd),
     .rd_en(rd_en),
     .data_rd(data_rd),
     .rd_empty(rd_empty),
     .wr_full(wr_full)
     );

     initial begin
         rst_n_rd = ;
         rst_n_wr = ;
         clk_wr = ;
         clk_rd = ;
         wr_en = ;
         rd_en = ;

         #
         rst_n_rd = ;
         rst_n_wr = ;

         #
         wr_en = ;
         rd_en = ;

         #
         wr_en = ;
         rd_en = ;
     end

     always # clk_wr = ~clk_wr;
     always # clk_rd = ~clk_rd;

 /*     always @(posedge clk_rd)
         rd_en <= ($random) % 2;

     always @(posedge clk_wr)
         wr_en <= ($random) % 2; */

     always @(posedge clk_wr)
         data_wr <= ($random) % ;

 endmodule

Asyn_FIFO_tb.v

 module Asyn_FIFO
 #(
     parameter WIDTH = ,
     parameter DEPTH =
 )
 (
     input  clk_wr,
     input  clk_rd,
     input  rst_n_rd,
     input  rst_n_wr,
     input  wr_en,
     input  rd_en,
     input  [WIDTH-:] data_wr,
     output [WIDTH-:] data_rd,
     output reg rd_empty,
     output reg wr_full
 );

     //defination
     reg  [WIDTH- : ] mem [ : (<<DEPTH)-];        //2^DEPTH numbers
     reg  [DEPTH   : ] wp, rp;
     reg  [DEPTH   : ] wr1_rp, wr2_rp, rd1_wp, rd2_wp;
     reg  [DEPTH   : ] wbin, rbin;

     wire [DEPTH- : ] waddr, raddr;
     wire [DEPTH   : ] wbin_next, rbin_next;        //bincode
     wire [DEPTH   : ] wgray_next, rgray_next;        //graycode

     wire rd_empty_val, wr_full_val;

     //output
     assign data_rd = (rd_en && !rd_empty) ? mem[raddr] : ;        //clear "xx" state

     //input
     always@(posedge clk_wr)
         if(wr_en && !wr_full)
             mem[waddr] <= data_wr;

 /*----------generate waddr and raddr-------------------------*/
     //gen raddr and read gray code
     always@(posedge clk_rd or negedge rst_n_rd)
         if(!rst_n_rd)
             {rbin, rp} <= ;
         else
             {rbin, rp} <= {rbin_next, rgray_next};

     assign raddr = rbin[DEPTH- : ];
     assign rbin_next = rbin + (rd_en & ~rd_empty);
     assign rgray_next = rbin_next ^ (rbin_next >> );

     //gen waddr and write gray code
     always@(posedge clk_wr or negedge rst_n_wr)
         if(!rst_n_wr)
             {wbin, wp} <= ;
         else
             {wbin, wp} <= {wbin_next, wgray_next};

     assign waddr = wbin[DEPTH- : ];
     assign wbin_next = wbin + (wr_en & ~wr_full);
     assign wgray_next = wbin_next ^ (wbin_next >> );

 /*---------------synchro rp and wp--------------------------*/
     //synchro rp
     always@(posedge clk_wr or negedge rst_n_wr)
         if(!rst_n_wr)
             {wr2_rp, wr1_rp} <= ;
         else
             {wr2_rp, wr1_rp} <= {wr1_rp, rp}; //delay two clock

     //synchro wp
     always@(posedge clk_rd or negedge rst_n_rd)
         if(!rst_n_rd)
             {rd2_wp, rd1_wp} <= ;
         else
             {rd2_wp, rd1_wp} <= {rd1_wp, wp};

 /*---------------empty and full flags--------------------------*/
     //gen rd_empty
     assign rd_empty_val = (rd2_wp == rgray_next);
     always@(posedge clk_rd or negedge rst_n_rd)
         if(!rst_n_rd)
             rd_empty <= 'b1;
         else
             rd_empty <= rd_empty_val;

     //gen wr_full, two high bit do not equal
     assign wr_full_val = ({~wr2_rp[DEPTH : DEPTH-], wr2_rp[DEPTH- : ]} == wgray_next);
     always@(posedge clk_wr or negedge rst_n_wr)
         if(!rst_n_wr)
             wr_full <= 'b0;
         else
             wr_full <= wr_full_val;

 endmodule

Asyn_FIFO.v

注意wire、reg类型的赋值。