clock gate的cell多采用latch的形式,来实现,尽可能避免glitch的产生. 可以的verilog建模方式: module cell_ckgate(TE,E,CP,Q) input TE; input E; input CP; output Q; wire E_or; wire E_lat; assign E_or = E | TE; always @(CP or E_or) if (!CP) begin E_lat <= E_or; end assign Q=E_lat &am…