A method of handling processor to processor interrupt requests in a multiprocessing computer bus environment is described. This method allows a multiple-tiered, increasing priority, interrupt request scheme. This method also allows processor to proce…

A computer system is described having one or more host processors, a host chipset and an input/output (I/O) subsystem. The host processors are connected to the host chipset by a host bus. The host chipset is connected to the input/output subsystem by…

BACKGROUND OF THE INVENTION This relates to Input/Output (I/O) performance in a host system having multiple processors, and more particularly, to efficient usage of multiple processors in handling I/O completions by using interrupt affinity schemes t…

http://en.wikipedia.org/wiki/Motherboard_form_factor Computer form factor From Wikipedia, the free encyclopedia   (Redirected from Motherboard form factor)   For computers form factors both larger and smaller than desktop personal computers, see list…

BACKGROUND The present disclosure relates to the handling of interrupts in a environment that utilizes virtual machines, and, more specifically, to the steering of interrupts between multiple logical processors running virtual machines. The virtualiz…

Within a multi-processing system including a plurality of processor cores 4, 6operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region.…

A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC n…

Copied From:https://computing.llnl.gov/tutorials/parallel_comp/ Author: Blaise Barney, Lawrence Livermore National Laboratory UCRL-MI-133316 Table of Contents Abstract Overview What is Parallel Computing? Why Use Parallel Computing? Who is Using Para…

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals…

BACKGROUND The present disclosure relates to the resource management of virtual machine(s) using hardware address mapping, and, more specifically, to facilitate direct access to devices from virtual machines, utilizing control of hardware address tra…