总线读写---verilog代码

总线读写---verilog代码

 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
 // Company:
 // Engineer: chensimin
 //
 // Create Date: 2017/11/16 17:32:35
 // Design Name:
 // Module Name: read_and_write
 // Project Name:
 // Target Devices:
 // Tool Versions:
 // Description:
 //
 // Dependencies:
 //
 // Revision:
 // Revision 0.01 - File Created
 // Additional Comments:
 //
 //////////////////////////////////////////////////////////////////////////////////

 module read_and_write(

 //-----------------------clock and reset--------------------------
     input  wire       clk,
     input  wire       reset,
 //-----------------------up_interface---------------------------
     input  wire [:]up_address_channel,
     input  wire [:]up_wdata,
     output wire [:]up_rdata,
     input  wire       up_read_en,
     input  wire       up_write_en,
     output wire       up_ack,
 //--------------------device IPC interface------------------------
     input  wire       ipc_ack,
     input  wire [:]ipc_rdata,
     output wire [:]ipc_wdata,
     output wire       ipc_rd,
     output wire       ipc_wr,
     output wire [:]ipc_addr,
 //--------------------------channel-------------------------------
     input  wire       channel_sel,
 //--------------------read flag-----------------------------------
     output wire       read_start_w
     );

 //------------------------read------------------------------------
 reg ipc_rd_r;
 reg [:]ipc_addr_r;
 reg ipc_wr_r;
 reg [:]ipc_wdata_r;
 reg [:]ipc_rdata_r;
 reg read_start;
 reg read_done;
 reg write_done;
 reg [:]i;
 reg [:]j;
 reg get_read_address;
 reg get_write_address;
 reg up_read_en_delay;
 reg up_write_en_delay;

 always @ (posedge clk or posedge reset)
     if(reset)
     begin
         up_read_en_delay <= 'b0;
         up_write_en_delay <= 'b0;
     end
     else
     begin
         up_read_en_delay <= up_read_en;
         up_write_en_delay <= up_write_en;
     end

 always @ (posedge clk or posedge reset)
     if(reset)
     begin
         ipc_rd_r <= 'b0;
         ipc_rdata_r <= 'h00000000;
         read_start <= 'b0;
         read_done <= 'b0;
         i <= 'd0;
         get_read_address <= 'b0;
     end
     else
     begin
         read_start <= 'b0;
         read_done <= 'b0;
         ipc_rd_r <= 'b0;
         get_read_address <= 'b0;
         case(i)
         'd0:
         begin
             if(channel_sel && up_read_en_delay)
             begin
                 get_read_address <= 'b1;
                 i <= i + 'b1;
             end
             else
                 i <= 'd0;
         end
         'd1:
         begin
             if(!ipc_ack)
                 ipc_rd_r <= 'b1;
             else
             begin
                 ipc_rdata_r <= ipc_rdata;
                 read_start <= 'b1;
                 read_done <= 'b1;
                 i <= i + 'b1;
             end
         end
         'd2:
         begin
             if(channel_sel && !up_read_en_delay)
                 i <= 'd0;
             else
                 i <= 'd2;
         end
         default:
         begin
             i <= 'd0;
             read_start <= 'b0;
             read_done <= 'b0;
             ipc_rd_r <= 'b0;
             get_read_address <= 'b0;
         end
         endcase
     end
 //------------------------write--------------------------------
 always @ (posedge clk or posedge reset)
     if(reset)
     begin
         ipc_wr_r <= 'b0;
         ipc_wdata_r <= 'h00000000;
         write_done <= 'b0;
         j <= 'd0;
         get_write_address <= 'b0;
     end
     else
     begin
         write_done <= 'b0;
         ipc_wr_r <= 'b0;
         get_write_address <= 'b0;
         case(j)
         'd0:
         begin
             if(channel_sel && up_write_en_delay)
             begin
                 get_write_address <= 'b1;
                 ipc_wdata_r <= up_wdata;
                 j <= j + 'b1;
             end
             else
                 j <= 'd0;
         end
         'd1:
         begin
             if(!ipc_ack)
                 ipc_wr_r <= 'b1;
             else
             begin
                 write_done <= 'b1;
                 j <= j + 'b1;
             end
         end
         'd2:
         begin
             if(channel_sel && !up_write_en_delay)
                 j <= 'd0;
             else
                 j <= 'd2;
         end
         default:
         begin
             j <= 'd0;
             write_done <= 'b0;
             ipc_wr_r <= 'b0;
             get_write_address <= 'b0;
         end
         endcase
     end
 //-------------------up_ack signal--------------------------
 reg up_ack_r;
 always @ (posedge clk or posedge reset)
     if(reset)
         up_ack_r <= 'b0;
     else if(read_done || write_done)
         up_ack_r <= 'b1;
     else
         up_ack_r <= 'b0;

 assign up_ack = up_ack_r;

 //------------------drive addr output-------------------------
 always @ (posedge clk or posedge reset)
     if(reset)
         ipc_addr_r <= 'h000;
     else if(get_read_address || get_write_address)
     begin
         ipc_addr_r <= up_address_channel;
     end

 assign ipc_rd = ipc_rd_r;
 assign ipc_addr = ipc_addr_r;
 assign ipc_wdata = ipc_wdata_r;
 assign ipc_wr = ipc_wr_r;
 assign up_rdata = ipc_rdata_r;
 assign read_start_w = read_start;

 endmodule

备注：在进行总线写操作的时候，写地址和数据信号要先准备好，等待写使能信号的到来。

非常重要的两点需要注意：

1.外部输入的控制信号，（如使能信号）往往和clk不同步，这就需要在使用前做延时处理，使其同步，这需要根据调试情况来定。

2.使能信号的使用，使能信号往往是一种脉冲信号，即：一个高点平期间，只进行一次相应的操作（读或写），这就需要在状态机中对使能信号进行合理的运用。如状态机中最后的一个状态：

 'd2:
 begin
 if(channel_sel && !up_read_en_delay)
      i <= 'd0;
 else
      i <= 'd2;
 end

 'd2:
 begin
  if(channel_sel && !up_write_en_delay)
      j <= 'd0;
  else
      j <= 'd2;
 end

当使能信号执行完一个状态机后拉低时，状态机回到初始状态；

当使能信号执行完一个状态机后依旧保持高电平，状态机依旧保持当前状态。

这就是一个使能脉冲，执行一次操作的控制方法。