Verilog从文件读数据

reg start;
reg [17:0] counter;
always @(posedge i_clk)//置rst、start
begin
//产生读数据地址
　　if(counter==171519||start==1)
　　begin
　　　　counter <=0;
　　end
　　else
　　begin
　　　　counter <= counter + 1;
　　end
end

integer fid_in_I,fid_in_Q;
reg signed [15:0] data_in_int_I;
reg signed [15:0] data_in_int_Q;
wire signed [15:0] i_Data_I_into_EstEqu;
wire signed [15:0] i_Data_Q_into_EstEqu;
assign i_Data_I_into_EstEqu = data_in_int_I;
assign i_Data_Q_into_EstEqu = data_in_int_Q;

initial
begin
　　fid_in_I = $fopen("E:/Signal_real.txt","r");
　　fid_in_Q = $fopen("E:/Signal_imag.txt","r");
end

always @ (posedge i_clk || !i_rst_n)
begin
　　if(counter==2560*67-1||start==1)
　　begin
　　　　$fseek(fid_in_I,0,0);
　　　　$fseek(fid_in_Q,0,0);
　　end
　　$fscanf(fid_in_I,"%d",data_in_int_I);
　　$fscanf(fid_in_Q,"%d",data_in_int_Q);
end