基于Verilog的带FIFO写入缓冲的串口发送接口封装

一、模块框图及基本思路

tx_module：串口发送的核心模块，详细介绍请参照前面的“基于Verilog的串口发送实验”

fifo2tx_module：当fifo不为空时，读取fifo中的数据并使能发送

tx_fifo：深度为1024,8位宽度fifo

tx_interface：前面几个模块的组合

tx_interface_control：不断向tx_fifo中写入递增的8位数据（8’d0-8’hff）

tx_interface_top：顶层模块

二、软件部分

tx_bps_module:

 module tx_bps_module #(parameter Baud=)(
     CLK,RSTn,
     Count_Sig,
     BPS_CLK
     );
     input CLK;
     input RSTn;
     input Count_Sig;
     output BPS_CLK;

     /***************************/
     localparam Baud_Div=50_000_000/Baud-;
     localparam Baud_Div2=Baud_Div/;

     reg[:] Count_BPS;
     /*************************/
     always @(posedge CLK or negedge RSTn)
     begin
         if(!RSTn)
             Count_BPS<='d0;
         else if(Count_BPS==Baud_Div)
             Count_BPS<='d0;
         else if(Count_Sig)
             Count_BPS<=Count_BPS+;
         else Count_BPS<='d0;
     end
     /************************/
     assign BPS_CLK=(Count_BPS==Baud_Div2)?'b1:1'b0;
 endmodule

tx_control_module:

 module tx_control_module(
     CLK,RSTn,
     TX_En_Sig,TX_Data,BPS_CLK,
     TX_Done_Sig,TX_Pin_Out
     );
     input CLK,RSTn;
     input TX_En_Sig,BPS_CLK;
     input [:]TX_Data;
     output TX_Done_Sig,TX_Pin_Out;
     /***************************************/
     reg rTX;
     reg isDone;
     reg[:] i;
     always @(posedge CLK or negedge RSTn)
     begin
         if(!RSTn)
         begin
             rTX<='b1;
             isDone<='b0;
             i<='d0;
         end
         else if(TX_En_Sig)
         begin
             case(i)
             'd0:if(BPS_CLK) begin rTX<=0;i<=i+1'b1; end
             'd1,4'd2,'d3,4'd4,'d5,4'd6,'d7,4'd8:
             if(BPS_CLK) begin rTX<=TX_Data[i-];i<=i+'b1; end
             'd9:if(BPS_CLK) begin rTX<=1;i<=i+1'b1; end
             'd10:if(BPS_CLK) begin rTX<=1;i<=i+1'b1; end
             'd11:if(BPS_CLK) begin isDone<=1;i<=i+1'b1; end
             'd12: begin isDone<=0;i<=1'b0; end
             endcase
         end
     end
     /***************************************/
     assign TX_Pin_Out=rTX;
     assign TX_Done_Sig=isDone;
 endmodule

tx_module:

module tx_module(
    CLK,RSTn,
    TX_En_Sig,TX_Data,TX_Pin_Out,TX_Done_Sig
    );
    input CLK;
    input RSTn;
    input TX_En_Sig;
    input [:] TX_Data;
    output TX_Pin_Out;
    output TX_Done_Sig;

    wire BPS_CLK;

    tx_bps_module U0(.CLK(CLK),.RSTn(RSTn),.Count_Sig(TX_En_Sig),.BPS_CLK(BPS_CLK));
    tx_control_module U1(.CLK(CLK),.RSTn(RSTn),.TX_En_Sig(TX_En_Sig),
                    .BPS_CLK(BPS_CLK),.TX_Data(TX_Data),.TX_Done_Sig(TX_Done_Sig),
                    .TX_Pin_Out(TX_Pin_Out));
endmodule

fifo2tx_module:

 module fifo2tx_module(
     input CLK,
     input RSTn,
     //fifo接口
     input Empty_Sig,
     input [:] FIFO_Read_Data,
     output Read_Req_Sig,
     //tx_module接口
     input TX_Done_Sig,
     output [:]TX_Data,
     output TX_En_Sig
     );

      /*************************************************/
      reg isRead;
      reg isTX;
      reg [:]i;
      always @(posedge CLK or negedge RSTn)
      if(!RSTn)
      begin
         i<='d0;
         isRead<='b0;
         isTX<='b0;
      end
      else
      case(i)
      'd0:if(!Empty_Sig) begin isRead<=1'b1;i<=i+'b1; end
      'd1:begin isRead<=1'b0;i<=+'b1; end
      'd2:if(TX_Done_Sig) begin isTX<=1'b0;i<='d0; end
             else isTX<='b1;
      endcase
      /************************************************/
      assign Read_Req_Sig=isRead;
      assign TX_En_Sig=isTX;
      assign TX_Data=FIFO_Read_Data;

 endmodule

tx_interface:

 module tx_interface(
     input CLK,
     input RSTn,
     //FIFO写入接口
     input Write_Req_Sig,
     input [:]FIFO_Write_Data,
     output Full_Sig,

     output TX_Pin_Out
     );

      wire Empty_Sig;
      wire Read_Req_Sig;
      wire [:] FIFO_Read_Data;

     wire TX_En_Sig;
     wire TX_Done_Sig;
     wire [:]TX_Data;

 tx_fifo U0 (
   .clk(CLK), // input clk
   .rst(!RSTn), // input rst
   .din(FIFO_Write_Data), // input [7 : 0] din
   .wr_en(Write_Req_Sig), // input wr_en
   .rd_en(Read_Req_Sig), // input rd_en
   .dout(FIFO_Read_Data), // output [7 : 0] dout
   .full(Full_Sig), // output full
   .empty(Empty_Sig) // output empty
 );

     fifo2tx_module U1 (
     .CLK(CLK),
     .RSTn(RSTn),
     .Empty_Sig(Empty_Sig),
     .FIFO_Read_Data(FIFO_Read_Data),
     .Read_Req_Sig(Read_Req_Sig),
     .TX_Done_Sig(TX_Done_Sig),
     .TX_Data(TX_Data),
     .TX_En_Sig(TX_En_Sig)
 );

     tx_module U2 (
     .CLK(CLK),
     .RSTn(RSTn),
     .TX_En_Sig(TX_En_Sig),
     .TX_Data(TX_Data),
     .TX_Pin_Out(TX_Pin_Out),
     .TX_Done_Sig(TX_Done_Sig)
 );

 endmodule

tx_interface_control:

 module tx_interface_control(
     input CLK,
     input RSTn,
     output Write_Req_Sig,
     output [:]FIFO_Write_Data,
     input Full_Sig
     );

      /*****************FIFO写入部分********************/
     reg [:] i;
     reg Write_Req_Sig_r;
     reg [:]FIFO_Write_Data_r;

     always @(posedge CLK or negedge RSTn)
     if(!RSTn)
     begin
         FIFO_Write_Data_r<='d0;
         i<='d0;
         Write_Req_Sig_r<='b0;
     end
     else if(!Full_Sig)
     case(i)
         'd0:begin FIFO_Write_Data_r<=FIFO_Write_Data_r+1'b1;i<=i+'b1;Write_Req_Sig_r<=1'b1;end
         'd1:begin i<=2'd0;Write_Req_Sig_r<='b0;end
     endcase
      assign Write_Req_Sig=Write_Req_Sig_r;
      assign FIFO_Write_Data=FIFO_Write_Data_r;

 endmodule

tx_interface_top：

 module tx_interface_top(
     input CLK,
     input RSTn,
     output TX_Pin_Out
     );

     wire Write_Req_Sig;
     wire [:]FIFO_Write_Data;
     wire Full_Sig;

     tx_interface_control U0 (
     .CLK(CLK),
     .RSTn(RSTn),
     .Write_Req_Sig(Write_Req_Sig),
     .FIFO_Write_Data(FIFO_Write_Data),
     .Full_Sig(Full_Sig)
 );
     tx_interface U1 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Write_Req_Sig(Write_Req_Sig),
         .FIFO_Write_Data(FIFO_Write_Data),
         .Full_Sig(Full_Sig),
         .TX_Pin_Out(TX_Pin_Out)
     );

 endmodule

三、硬件部分

黑金SPARTAN开发板

 NET "CLK" LOC = T8;
 NET "RSTn" LOC = L3;
 NET "TX_Pin_Out" LOC = D12;