FPGA内部信号避免高阻态

RT，否则警告Warning: Tri-state node(s) do not directly drive top-level pin(s)，会利用或门代替中间的扇出fan-out.

原因：在进行FPGA设计时，对于FPGA内部的信号不能出现被赋值为高阻的状态，只有顶层的信号，即输出的信号才可以赋值为高阻态。

找出这个信号，然后把赋值为x'bz改为x'b0或x'b1(具体是改为x'b0还是x'b1要根据实际情况确定,x也行)。

CAUSE: The design contains tri-state nodes that drive non-tri-state logic, but the chip does not support internal tri-states. As a result, the Quartus II software converts all the tri-state nodes feeding internal logic to an equivalent logic.

ACTION: Avoid this warning by either removing the non-tri-state fan-outs of the affected tri-state nodes or replacing the tri-state nodes with non-tri-state logic.

实例：

module tri_state (input oe1, data1, in, output out, output bidir);

wire tribuf;

assign tribuf = oe1 ? data1 : 1'bz;

and(out, in, tribuf);

assign bidir = tribuf;

endmodule

Warning: Tri-state node(s) do not directly drive top-level pin(s)

       Warning: Converted the fan-out from the tri-state buffer "tribuf" to the node "comb" into an OR gate

RTL视图：

Technology Map Viewer:

CAUSE:The specified tri-statebuffer feeds internal logic in addition to  feeding tri-statelogic, but the chip does not support internal tri-states. As a result, the  Quartus II software converts the non-tri-statefan-out(s) of the tri-statebuffer to an  ORgate.

Consider the following design:
module test1 (input oe1, data1, in,  output out, inout bidir); 
wire tribuf, tmp; 
assign tribuf = oe1 ? data1  : 1'bz; 
and(tmp, in, tribuf); 
assign bidir = tribuf; 
assign out =  tmp; 
endmodule 
Here, the tri-statebuffer  tribufhas fan-outs to both the tri-stateand non-tri-statenodes. As a  result, the fan-out to the non-tri-statenode is converted to !oe1 +  data1.
Note that an inversion also counts as non-tri-statelogic. So, the  node tribufin the design test2is also converted to  an ORgate.
module test2 (input oe1, data1, output out,  inout bidir); 
wire tribuf; 
assign tribuf = oe1 ? data1 : 1'bz; 
assign bidir = tribuf; 
assign out = !tribuf; 
endmodule 
Additionally, a tri-statebuffer feeding the output enable signal of  another tri-statebuffer is also converted to logic.
Consider the following Verilog  design:
module test3 (input oe1, data1, data2, inout bidir); 
wire  tribuf1, tribuf2; 
assign tribuf1 = oe1 ? data1 : 1'bz; 
assign tribuf2 =  tribuf1 ? data2 : 1'bz; 
assign bidir = tribuf2; 
endmodule 
Here, the tri-statebuffer tribuf1is converted to an  ORgate.

ACTION:Avoid this warning by either removing the non-tri-statefan-out of the  tri-statebuffer or  replacing the tri-statebuffer with non-tri-statelogic.