EDA课设-交通灯-Verilog版----FPGA--004

• 分得到析四个状态：

S1: 主干道（绿灯亮） ，支干道（亮红灯）；--40S

S1: 主干道 （黄灯亮） ，支干道（亮红灯）；--4S

S1: 主干道 （亮红灯），支干道（绿灯亮）；--20S

S1: 主干道 （亮红灯），支干道（黄灯亮）；--4S

代码：包括四部分：traffic_ligh_top（顶层例化）、traffic_light（交通灯控制部分）、led_input_display（把（交通灯控制部分的）数据打一拍（再送给74595））、led_74595_driver（串转并-进行显示）

仿真：代码及波形显示

• 代码编写

//---------------------------------------------------------------------------------------

• RTL Viewer

• traffic_ligh_top（顶层例化）

 /*-----------------------------------------------------------------------
 Author                        :        WHaoL
 Technology blogs            :        http://www.cnblogs.com/luckySuperman/
                                 :        http://blog.chinaaet.com/eWorld
 Email Address                :        liangwenhao0603@163.com
 Filename                        :        traffic_ligh_top.v
 Data                            :        2016-09-26
 Description                    :
 modification history        :
 Data            By                Version            Change Description
 =========================================================================
 16/9/26        WHaoL            1.0                Original
 =======================================================================*/
 `timescale 1ns/1ns
 module traffic_ligh_top
 (
     input                 clk,
     input                    rst_n,

     //matrix keyboard interface

     output                 led595_clk,
     output                led595_dout,
     output                led595_latch
 );

 wire [:] led_east;
 wire [:] led_south;

 wire             key_flag;
 //-------------------------------------
  traffic_light  u_traffic_light
 (
             .clk(clk),    //时钟 50MHz
             .rst_n(rst_n),    //复位 低电平有效

             // south  north  east  west
             //.e_light(e_light),     // 东方向 指示灯
             //w_light,        //西方向 指示灯

             //.s_light(s_light),        //南方向 指示灯
             //n_light,        //北方向 指示灯
             .led_east(led_east),
             //.led_wast(led_wast),

             .led_south(led_south),
             //.led_nouth(led_nouth)
             .key_flag(key_flag)
 );                 

 //---------------------------------
 //led data input with enable signal.
 wire    [:]    led_data;
 led_input_display
 #(
     .LED_WIDTH    ()
 )
 u_led_input_display
 (
     //global
     .clk                    (clk),
     .rst_n                (rst_n),

     //user interface
     .led_en                (key_flag),
     .led_value            ({led_east[:],'b00,led_south[2:0]}),

     //led interface
     .led_data            (led_data)
 );

 //-------------------------------------------
 led_74595_driver    u_led_74595_driver
 (
     //global clock
     .clk                    (clk),//50MHz
     .rst_n                (rst_n),

     //user led output
     .led_data            (led_data),
     .led595_clk            (led595_clk),
     .led595_dout        (led595_dout),
     .led595_latch        (led595_latch)
 );

 endmodule

• traffic_light（交通灯控制部分）

 `timescale 1ns/1ns
 module traffic_light
 (
         clk,
         rst_n,

         key_flag,

         led_east,
         //led_wast,

         led_south
         //led_nouth

 );
 parameter     TIME_1S = 50_000_000;

 input         clk;
 input            rst_n;

 output        [:]        led_east;
 //output        [2:0]        led_wast;
 output        [:]        led_south;
 //output        [2:0]        led_nouth;
 output                    key_flag;

 reg        [:]        led_east;
 //reg        [2:0]        led_wast;
 reg        [:]        led_south;
 //reg        [2:0]        led_nouth;

 reg                    key_flag;

 reg         [:] cnt;
 reg       [:]  cnt_l;

 //---------------------------------------------------------
 //led_east
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         led_east <= 'b001;//G
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_east <= 'b010;//Y
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_east <= 'b100;//R
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_east <= 'b001;//G
     else
         led_east <= led_east;
 end 

 //---------------------------------------------------------
 //wast
 //always@(posedge clk or negedge rst_n)
 //begin
 //    if(!rst_n)
 //        led_wast <= 3'b001;
 //    else if((cnt_l == 39)&&(cnt == TIME_1S-1'b1))
 //        led_wast <= 3'b010;
 //    else if((cnt_l == 43)&&(cnt == TIME_1S-1'b1))
 //        led_wast <= 3'b100;
 //    else if((cnt_l == 67)&&(cnt == TIME_1S-1'b1))
 //        led_wast <= 3'b001;
 //    else
 //        led_wast <= led_wast;
 //end
 //---------------------------------------------------------/////////////////////////////////////
 //led_south
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         led_south <= 'b100;//R
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_south <= 'b001;//G
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_south <= 'b010;//Y
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_south <= 'b100;//R
     else
         led_south <= led_south;
 end
 //---------------------------------------------------------
 //led_nouth
 //always@(posedge clk or negedge rst_n)
 //begin
 //    if(!rst_n)
 //        led_nouth <= 3'b100;//R
 //    else if((cnt_l == 43)&&(cnt == TIME_1S-1'b1))
 //        led_nouth <= 3'b001;//G
 //    else if((cnt_l == 63)&&(cnt == TIME_1S-1'b1))
 //        led_nouth <= 3'b010;//Y
 //    else if((cnt_l == 67)&&(cnt == TIME_1S-1'b1))
 //        led_nouth <= 3'b100;//R
 //    else
 //        led_nouth <= led_nouth;
 //end
 //----------------------------------------------------------
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         cnt <= ;
     else if(cnt==(TIME_1S-'b1))
        cnt <= ;
     else
         cnt <= cnt+'b1;
 end

 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         cnt_l <= ;
     else if((cnt==(TIME_1S-'b1))&&(cnt_l==8'd67))
        cnt_l <= ;
     else if(cnt==(TIME_1S-'b1))
         cnt_l <= cnt_l+'b1;
     else
         cnt_l <= cnt_l;
 end

 //----------------------------------------------------------------------------
 //wire    key_trigger = ((cnt==TIME_1S-1'b1)&&((cnt_l==8'd39)||(cnt_l==8'd43)||(cnt_l==8'd67)||(cnt_l==8'd63))) ? 1'b1 : 1'b0;    

 wire    key_trigger = (cnt==(TIME_1S-'b1)) ? 1'b1 : 'b0;
 //---------------------------------
 //Lag 1 clock for valid read enable
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         key_flag <= ;
     else
         key_flag <= key_trigger;
 end

 endmodule

• led_input_display（把（交通灯控制部分的）数据打一拍（送给74595））

 `timescale 1ns/1ns
 module led_input_display
 #(
     parameter LED_WIDTH =
 )
 (
     //global clock
     input                                clk,
     input                                rst_n,

     //user interface
     input                                led_en,
     input        [LED_WIDTH-:]    led_value,

     //led interface
     output    reg    [LED_WIDTH-:]    led_data
 );

 //--------------------------------------
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         led_data <= 'b001_00_100;
     else if(led_en)
         led_data <= led_value;
     else
         led_data <= led_data;
 end

 endmodule

• led_74595_driver（串转并-进行显示）

 `timescale 1ns/1ns
 module led_74595_driver
 (
     //global clock
     input                clk,//50MHz
     input             rst_n,

     //user led output
     input    [:]    led_data,

     output            led595_clk,
     output            led595_dout,
     output            led595_latch
 );
 //-----------------------------
 //update display when led_data is update
 //generate led_data_r and  update_flag
 reg        [:]            led_data_r;
 reg                        update_flag;
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         begin
             led_data_r  <= ;
             update_flag <= ;
         end
     else
         begin
             led_data_r  <= led_data;
             update_flag <= (led_data_r == led_data)?'b1:1'b0;
         end
 end
 //------------------------------
 //74HC595 clk delay for enough setup time
 // generate shift_flag and shift_clk
 localparam                 DELAY_CNT = 'd7;
 reg                        shift_state;
 reg        [:]            delay_cnt;
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
             delay_cnt <= ;
     else if(shift_state == 'b1)
             delay_cnt <= (delay_cnt < DELAY_CNT) ? (delay_cnt+'b1):3'd0;
     else
             delay_cnt <= ;
 end
 wire shift_clk  = (delay_cnt  > DELAY_CNT/) ? 'b1 : 1'b0;
 wire shift_flag = (delay_cnt == DELAY_CNT)   ? 'b1 : 1'b0;
 //----------------------------------------
 //74HC595 shift data output state
 reg [:] led_cnt;
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         begin
             shift_state <= ;
             led_cnt <= ;
         end
     else
         begin
             case(shift_state)
             :        begin
                         led_cnt <= ;
                         if(update_flag)
                             shift_state <= 'b1;
                         else
                             shift_state <= ;
                     end
             :        begin
                         if(shift_flag)
                             begin
                                 if(led_cnt < 'd8)
                                     begin
                                     led_cnt <= led_cnt + 'b1;
                                     shift_state <= 'd1;
                                     end
                                 else
                                     begin
                                     led_cnt <= ;
                                     shift_state <= ;
                                     end
                                 end
                             else
                                 begin
                                 led_cnt <= led_cnt;
                                 shift_state <= shift_state;
                                 end
                     end
             endcase
         end
 end
 assign led595_dout  = (led_cnt < 'd8&&shift_state == 1'b1) ? led_data['d7-led_cnt]: 1'b0;
 assign led595_clk   = (led_cnt < 'd8&&shift_state == 1'b1) ? shift_clk : 'b0;
 assign led595_latch = (led_cnt =='d8&&shift_state == 1'b1) ? 'b1 : 1'b0;

 endmodule

• 仿真

//-----------------------------------------------------------------------------------------

• 仿真代码--第一部分 --traffic_light

 `timescale 1ns/1ns
 module traffic_light
 (
         clk,
         rst_n,

     //key_flag，
         led_east,
         //led_wast,

         led_south
         //led_nouth

 );
 parameter     TIME_1S = ;

 input         clk;
 input            rst_n;

 output        [:]        led_east;
 //output        [2:0]        led_wast;
 output        [:]        led_south;
 //output        [2:0]        led_nouth;
 //output                    key_flag;

 reg        [:]        led_east;
 //reg        [2:0]        led_wast;
 reg        [:]        led_south;
 //reg        [2:0]        led_nouth;

 //reg                    key_flag;

 reg         [:] cnt;
 reg       [:]  cnt_l;

 //---------------------------------------------------------
 //led_east
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         led_east <= 'b001;//G
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_east <= 'b010;//Y
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_east <= 'b100;//R
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_east <= 'b001;//G
     else
         led_east <= led_east;
 end 

 //---------------------------------------------------------
 //wast
 //always@(posedge clk or negedge rst_n)
 //begin
 //    if(!rst_n)
 //        led_wast <= 3'b001;
 //    else if((cnt_l == 39)&&(cnt == TIME_1S-1'b1))
 //        led_wast <= 3'b010;
 //    else if((cnt_l == 43)&&(cnt == TIME_1S-1'b1))
 //        led_wast <= 3'b100;
 //    else if((cnt_l == 67)&&(cnt == TIME_1S-1'b1))
 //        led_wast <= 3'b001;
 //    else
 //        led_wast <= led_wast;
 //end
 //---------------------------------------------------------/////////////////////////////////////
 //led_south
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         led_south <= 'b100;//R
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_south <= 'b001;//G
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_south <= 'b010;//Y
     else if((cnt_l == )&&(cnt == TIME_1S-'b1))
         led_south <= 'b100;//R
     else
         led_south <= led_south;
 end
 //---------------------------------------------------------
 //led_nouth
 //always@(posedge clk or negedge rst_n)
 //begin
 //    if(!rst_n)
 //        led_nouth <= 3'b100;//R
 //    else if((cnt_l == 43)&&(cnt == TIME_1S-1'b1))
 //        led_nouth <= 3'b001;//G
 //    else if((cnt_l == 63)&&(cnt == TIME_1S-1'b1))
 //        led_nouth <= 3'b010;//Y
 //    else if((cnt_l == 67)&&(cnt == TIME_1S-1'b1))
 //        led_nouth <= 3'b100;//R
 //    else
 //        led_nouth <= led_nouth;
 //end
 //----------------------------------------------------------
 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         cnt <= ;
     else if(cnt==(TIME_1S-'b1))
        cnt <= ;
     else
         cnt <= cnt+'b1;
 end

 always@(posedge clk or negedge rst_n)
 begin
     if(!rst_n)
         cnt_l <= ;
     else if((cnt==(TIME_1S-'b1))&&(cnt_l==8'd67))
        cnt_l <= ;
     else if(cnt==(TIME_1S-'b1))
         cnt_l <= cnt_l+'b1;
     else
         cnt_l <= cnt_l;
 end

 //----------------------------------------------------------------------------
 //wire    key_trigger = ((cnt==TIME_1S-1'b1)&&((cnt_l==8'd39)||(cnt_l==8'd43)||(cnt_l==8'd67)||(cnt_l==8'd63))) ? 1'b1 : 1'b0;    

 //wire    key_trigger = (cnt==(TIME_1S-1'b1)) ? 1'b1 : 1'b0;
 //---------------------------------
 //Lag 1 clock for valid read enable
 //always@(posedge clk or negedge rst_n)
 //begin
 //    if(!rst_n)
 //        key_flag <= 0;
 //    else
 //        key_flag <= key_trigger;
 //end

 endmodule

• 仿真代码--第二部分 --traffic_light_tb

 `timescale 1ns/1ns
 module traffic_light_tb;   

 //------------------------------------------
 //clock generate module
 reg    clk;
 reg    rst_n;
 localparam PERIOD = ;    //50MHz
 initial
 begin
     clk = ;
     forever    #(PERIOD/)
     clk = ~clk;
 end

 task task_reset;
 begin
     rst_n = ;
     repeat() @(negedge clk);
     rst_n = ;
 end
 endtask
 //------------------------------------------
 wire    [:]    led_east;
 wire [:]    led_south;
 traffic_light     u_traffic_light
                     (
                 .clk(clk),
                 .rst_n(rst_n), 

                 .led_east(led_east),
                 .led_south(led_south)
                     );    

 //---------------------------------------
 //system initialization
 task task_sysinit;
 begin
            // e_light = 3'b100; //?? R
          // s_light = 3'b001; //?? G
 end
 endtask

 //----------------------------------------
 //testbench of the RTL
 initial
 begin

     #;

     task_sysinit;
     task_reset;

 end

 endmodule 

• 仿真时序图