二段式fsm

1.推荐在敏感表下的默认状态为X，这样描述的好处有2个：

好处1：仿真易观察bug。

好处2：综合对不定态X的处理是"Don't Care",即任何没有定义的状态寄存器向量都会被忽略。

2.对于每个output,一般用combination描述，用task/endtask将output封装起来。

 //2-paragraph method to describe FSM
 //Describe sequential state transition in 1 sequential always block
 //State transition conditions in the other combinational always block
 //Package state output by task. Then register the output
 //Westor Wang, Dec. 2006
 //Verilog Training -- How to write FSM better

 module state2 (
                input nrst,
                input clk,
                input i1,
                input i2,
                output reg o1,
                output reg o2,
                output reg err
                );

 reg    [:]   NS,CS;

 parameter [:]      //one hot with zero idle
       IDLE   = 'b000,
       S1     = 'b001,
       S2     = 'b010,
       ERROR  = 'b100;

 //first paragraph:sequential state transition
 always @ (posedge clk or negedge nrst)
       if (!nrst)
          CS <= IDLE;
       else
          CS <=NS;           

 //second paragraph:combinational condition judgment
 always @ (nrst or CS or i1 or i2)
           begin
                NS = 'bx;  //default state  x
                ERROR_out;
                case (CS)
                     IDLE:     begin
                                    IDLE_out;
                                    if (~i1)           NS = IDLE;
                                    if (i1 && i2)      NS = S1;
                                    if (i1 && ~i2)     NS = ERROR;
                               end
                     S1:       begin
                                    S1_out;
                                    if (~i2)           NS = S1;
                                    if (i2 && i1)      NS = S2;
                                    if (i2 && (~i1))   NS = ERROR;
                               end
                     S2:       begin
                                    S2_out;
                                    if (i2)            NS = S2;
                        if (~i2 && i1)     NS = IDLE;
                                    if (~i2 && (~i1))  NS = ERROR;
                               end
                     ERROR:    begin
                                    ERROR_out;
                                    if (i1)            NS = ERROR;
                                    if (~i1)           NS = IDLE;
                               end
                endcase
          end

 //package output with task
 task IDLE_out;
      {o1,o2,err} = 'b000;
 endtask

 task S1_out;
      {o1,o2,err} = 'b100;
 endtask

 task S2_out;
      {o1,o2,err} = 'b010;
 endtask

 task ERROR_out;
      {o1,o2,err} = 'b111;
 endtask

 endmodule

 注意：并不是有reg就是时序逻辑，触发器。针对FSM的output组合逻辑。