三段式fsm

1.状态转移的always中CS，同步ouput的always中NS。

2.3段fsm vs 2段fsm：output逻辑是组合逻辑和同步时序逻辑（消除里不稳的和毛刺）。

3.3段fsm vs 1段fsm: output都是同步时序逻辑，直接根据NS描述output和另外还要考虑状态转移条件描述output。

4.段式划分不是数always个数，而是每种段式对应有固定的描述内容和格式化的结构。强调的是建模思路。

5.3段fsm，解决了2段fsm中不改变时序要求的前提下用寄存器做状态输出的问题。

 //3-paragraph method to describe FSM
 //Describe sequential state transition in the 1st sequential always block
 //State transition conditions in the 2nd combinational always block
 //Describe the FSM out in the 3rd sequential always block
 //Westor Wang, Dec. 2006
 //Verilog Training -- How to write FSM better

 module state3 (
                 input nrst,
                 input clk,
                 input i1,
                 input i2,
                 output reg o1,
                 output reg o2,
                 output reg err
                );

 reg    [:]   NS,CS;

 parameter [:]      //one hot with zero idle
       IDLE   = 'b000,
       S1     = 'b001,
       S2     = 'b010,
       ERROR  = 'b100;

 //1st always block, sequential state transition
 always @ (posedge clk or negedge nrst)
       if (!nrst)
          CS <= IDLE;
       else
          CS <=NS;           

 //2nd always block, combinational condition judgment
 always @ (nrst or CS or i1 or i2)
           begin
                NS = 'bx;
                case (CS)
                     IDLE:     begin
                                    if (~i1)           NS = IDLE;
                                    if (i1 && i2)      NS = S1;
                                    if (i1 && ~i2)     NS = ERROR;
                               end
                     S1:       begin
                                    if (~i2)           NS = S1;
                                    if (i2 && i1)      NS = S2;
                                    if (i2 && (~i1))   NS = ERROR;
                               end
                     S2:       begin
                                    if (i2)            NS = S2;
                        if (~i2 && i1)     NS = IDLE;
                                    if (~i2 && (~i1))  NS = ERROR;
                               end
                     ERROR:    begin
                                    if (i1)            NS = ERROR;
                                    if (~i1)           NS = IDLE;
                               end
                endcase
          end

 //3rd always block, the sequential FSM output
 always @ (posedge clk or negedge nrst)
  if (!nrst)
       {o1,o2,err} <= 'b000;
  else
     begin
        {o1,o2,err} <=  'b000;
        case (NS)
            IDLE:  {o1,o2,err}<='b000;

            S1:    {o1,o2,err}<='b100;
            S2:    {o1,o2,err}<='b010;
            ERROR: {o1,o2,err}<='b111;
        endcase
     end

 endmodule