VHDL之FSM

1　　Intro

　　The figure shows the block diagram of a single-phase state machine. The lower section contains sequential logic (flip-flops), while the upper section contains combinational logic.

　　The combinational section has two inputs, pr_state (present state) and external input. It has also two outputs, nx_state (next state) and external output. The sequential section has three inputs (clock, reset, and nx_state), and one output (pr_state). Since all flip-flops are in this part of the system, clock and reset must be connected to it.

　　If the output of the machine depends not only on the present state but also on the current input, then it is called a Mealy machine. Otherwise, if it depends only on the current state, it is called a Moore machine. Examples of both will be shown later.

　　

2　　Design style (recommended)

　　1)　　Sequential　　

  process (reset, clock)
  begin
 　　if (reset = '') then
 　　　　pr_state <= state0;
 　　elsif (clock'event and clock = '') then
 　　　　pr_state <= nx_state;
  end if;
  end process;　

　　It consists of an asynchronous reset, which determines the initial state of the system (state0), followed by the synchronous storage of nx_state (at the positive transition of clock), which will produce pr_state at the lower section’s output (figure 8.1).

　　One good thing is that the design of the lower section is basically standard. Another advantage is that the number of registers is minimum.

　　

　　2)　　Combinational

　　

 process (input, pr_state)
 begin
 　　case pr_state is
 　　　　when state0 =>
 　　　　　　if (input = ...) then
 　　　　　　　　output <= <value>;
 　　　　　　　　nx_state <= state1;
 　　　　　　else ...
 　　　　　　end if;
 　　　　when state1 =>
 　　　　　　if (input = ...) then
 　　　　　　　　output <= <value>;
 　　　　　　　　nx_state <= state2;
 　　　　　　else ...
 　　　　　　end if;
16　　 　　when state2 =>
17　　 　　　　if (input = ...) then
 　　　　　　　　output <= <value>;
 　　　　　　　　nx_state <= state2;
 　　　　　　else ...
 　　　　　　end if;
 　　　　...
 　　end case;
 end process;

　　As can be seen, this code is also very simple, and does two things:

　　　(a) assign the output value

　　　(b) establish the next state.

3　　VHDL template　

 library ieee;
 use ieee.std_logic_1164.all;
 3 -----------------------------------------------------
 entity <entity_name> is
     port( input            : in <data_type>;
           reset, clock    : in std_logic;
           output        : out <data_type>);
 end <entity_name>;
 9 -----------------------------------------------------
 architecture <arch_name> of <entity_name> is
     type state is (state0, state1, state2, state3, ...);
     signal pr_state, nx_state: state;

 begin
15 ---------- Sequential  ------------------------
 process (reset, clock)
 begin
     if (reset='') then
         pr_state <= state0;
     elsif (clock'event and clock='') then
         pr_state <= nx_state;
     end if;
 end process;
24 ---------- Combinational ------------------------
 process (input, pr_state)
 begin
     case pr_state is
         when state0 =>
             if (input = ...) then
                 output <= <value>;
                 nx_state <= state1;
             else ...
             end if;
         when state1 =>
             if (input = ...) then
                 output <= <value>;
                 nx_state <= state2;
             else ...
             end if;
         when state2 =>
             if (input = ...) then
                 output <= <value>;
                 nx_state <= state3;
             else ...
             end if;
         ...
     end case;
 end process;

 end <arch_name>;