Rocket - 断句 - Diplomacy and TileLink from the Rocket Chip

https://mp.weixin.qq.com/s/rfgptF9YxDpzDoespYtQvA

 

整理Diplomacy and TileLink from the Rocket Chip这篇文章。

 

 

0. 原文链接

 

https://www.lowrisc.org/docs/diplomacy/

https://docs.qq.com/doc/DUUZsQlJIdmFqdHpQ

 

 

1. Introduction

 

a SoC [1]developed maintained configured coresRocket cores BOOM coresarchitecture are configurable .

individual settingsmaintaining is tough jobtraditional waydesign timeparameters and macros Scala-run-timenegotiationgeneration DiplomacyTileLink bus protocol(a) negotiation and checking(b)bus generation(c)interrupt connectionScala-run-time

 

2. Background Information

 

3. Extra Information About the Diplomacy Package

 

3.1 Diplomacy supports directed acyclic graphs

 

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• agents A hardware component may not be associated to any if it is not directly connected to an interconnect. A hardware component may have more than one if it is connected to more than one interconnects. Considering a DMA component, it may have one controlling its connection to the high-speed data bus while also has another controlling its connection to the configuration bus.
• links The DAG is built at Scala-run-time to negotiate the parameters of various . Although it is normally true that an represents a real communication in hardware, it is not necessary that the Diplomacy must produce the actual hardware connections for these . The DAG and the Diplomacy package can be hijacked to negotiating the parameters for a virtual network while the actually hardware connections are settled separately. This is how the Diplomacy package is extended for the shared SV AXI bus in lowRISC.

 

 

3.2 A rough description of the implementation of a Node

 

3.3 Cake pattern

 

4. lowRISC extension to support an external SystemVerilog AXI bus

 

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5. References

 

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