asyn_fifo

 //Module Name:afifo_ctrl
 //Description:parameterized afifo

 module afifo_ctrl(
   clk_push,
   rst_push_n,
   clk_pop,
   rst_pop_n,
   push,
   push_data,
   full,
   pop,
   pop_data,
   empty,
   mem_waddr,
   mem_wen,
   mem_wdata,
   mem_raddr,
   mem_ren,
   mem_rdata,
   almost_full
   );

 parameter DATAWIDTH = ;         //the data width of AFIFO
 parameter ADDRWIDTH = ;          //the address bits of AFIFO and it must be >=2
                                   //the AFIFO depth must be 2^ADDRWIDTH
 //input declaration
 input clk_push;                   //push clock
 input rst_push_n;                 //reset signal in push clock domain

 input clk_pop;                    //pop clock
 input rst_pop_n;                  //reset signal in pop clock domain
 input push ;                      //push enable to AFIFO
 input [DATAWIDTH-:]  push_data; //push data to AFIFO
 input pop  ;                      //pop enable to AFIFO
 input [DATAWIDTH-:]  mem_rdata; //read data from memory stack

 //output declaration
 output full;                      //full indicator,and the logic of user can't push data when this signal is high                                                           //ok
 output [DATAWIDTH-:] pop_data ; //pop data from AFIFO              //ok
 output empty;                     //empty indicator, and the logic of user can't pop data when this signal is high                                                           //ok
 output [ADDRWIDTH-:] mem_waddr; //write address to memory stack    //ok
 output mem_wen;                   //write enable to memory stack     //ok
 output [DATAWIDTH-:] mem_wdata; //write data to memory stack       //ok
 output [ADDRWIDTH-:] mem_raddr; //read address to memory stack     //ok
 output mem_ren;                   //read enable to memory stack      //ok
 output almost_full;

 //register declaration

 reg [ADDRWIDTH-:]  mem_waddr;
 reg [ADDRWIDTH-:]  mem_raddr;
 reg [ADDRWIDTH-:]  gray_waddr_1r;
 reg [ADDRWIDTH-:]  gray_waddr_2r_1_sync;
 reg [ADDRWIDTH-:]  gray_waddr_3r_2_sync;
 reg [ADDRWIDTH-:]  gray_raddr_1r;
 reg [ADDRWIDTH-:]  gray_raddr_2r_1_sync;
 reg [ADDRWIDTH-:]  gray_raddr_3r_2_sync;
 reg [ADDRWIDTH-:]  gray_waddr_temp;
 reg [ADDRWIDTH-:]  gray_raddr_temp;
 reg [ADDRWIDTH-:]  biny_waddr;
 reg [ADDRWIDTH-:]  biny_raddr;
 reg [ADDRWIDTH-:]  biny_waddr_temp;
 reg [ADDRWIDTH-:]  biny_raddr_temp;
 reg [DATAWIDTH-:]  pop_data_r;
 reg pop_r;
 reg empty_flag;
 reg full_flag;

 //net declaration
 wire mem_wen;
 wire mem_ren;
 wire [DATAWIDTH-:] mem_wdata;
 wire [DATAWIDTH-:] pop_data;
 wire [ADDRWIDTH-:] gray_waddr;
 wire [ADDRWIDTH-:] gray_raddr;
 wire pop_one_left;
 wire pop_ptr_diff;
 wire push_one_left;
 wire push_ptr_diff;

 integer i;

 assign mem_wen = push;
 assign mem_wdata[DATAWIDTH-:] = push_data[DATAWIDTH-:];
 assign mem_ren = pop;

 //for output signal pop_data
 always@(posedge clk_pop or negedge rst_pop_n)
 begin
   if(~rst_pop_n)
     pop_r<='b0;
   else
     pop_r<=pop;
 end

 always@(posedge clk_pop or negedge rst_pop_n)
 begin
   if(~rst_pop_n)
     pop_data_r[DATAWIDTH-:] <= ;
   else
     pop_data_r[DATAWIDTH-:] <= mem_rdata[DATAWIDTH-:];
 end

 assign pop_data[DATAWIDTH-:] = pop_r ? mem_rdata[DATAWIDTH-:]:pop_data_r[DATAWIDTH-:];

 //for output signal mem_waddr
 always@(posedge clk_push or negedge rst_push_n)
 begin
   if(~rst_push_n)
     mem_waddr[ADDRWIDTH-:] <=;
   else
     mem_waddr[ADDRWIDTH-:] <= mem_waddr[ADDRWIDTH-:] + 'b1;
 end

 //for output signal mem_raddr
 always@(posedge clk_pop or negedge rest_pop_n)
 begin
   if(~rst_pop_n)
     mem_raddr[ADDRWIDTH-:]<=;
   else
     mem_raddr[ADDRWIDTH-:] <= mem_raddr[ADDRWIDTH-:] + 'b1;
 end

 //for output signal empty
 assign gray_addr[ADDRWIDTH-:] = {mem_waddr[ADDRWIDTH-],gray_waddr_temp[ADDRWIDTH-:]};
 always@(* )
   for(i=;i<(ADDRWIDTH-);i=i+)
     gray_waddr_temp[i] = mem_waddr[i]^mem_waddr[i+];

 always@(posedge clk_push or negedge rst_push_n)
 begin
   if(~rst_push_n)
     gray_waddr_1r[ADDRWIDTH-:] <= ;
   else
     gray_waddr_1r[ADDRWIDTH-:] <= gray_waddr[ADDRWIDTH-:];
 end

 always@(posedge clk_pop or negedge rst_pop_n)
 begin
   if(~rst_pop_n) begin
     gray_waddr_2r_1_sync[ADDRWIDTH-:] <=;
     gray_waddr_3r_2_sync[ADDRWIDTH-:] <=;
   end
   else begin
      gray_waddr_2r_1_sync[ADDRWIDTH-:] <= gray_waddr_1r[ADDRWIDTH-:];
      gray_waddr_3r_2_sync[ADDRWIDTH-:] <= gray_waddr_2r_1_sync[ADDRWIDTH-:];
   end
 end

 always@(*)
   biny_waddr[ADDRWIDTH-] = gray_waddr_3r_2_sync[ADDRWIDTH-];

 always@(*)
   for(i=;i<(ADDRWIDTH-);i=i+)
     biny_waddr[ADDRWIDTH--i] = gray_waddr_3r_2_sync[ADDRWIDTH--i]^biny_waddr_temp[ADDRWIDTH--i];

 always@(*)
   biny_waddr_temp[ADDRWIDTH-:] = biny_waddr[ADDRWIDTH-:];

 assign pop_one_left = (biny_waddr[ADDRWIDTH-:] ==(mem_raddr[ADDRWIDTH-:] + 'b1));
 assign pop_ptr_diff = (biny_waddr[ADDRWIDTH-:] != mem_raddr[ADDRWIDTH-:]);

 always@(posedge clk_pop or negedge rst_pop_n)
 begin
   if(~rst_pop_n)
     empty_flag <='b1;
   else if(pop_one_left && pop)
     empty_flag <= 'b1;
   else if(empty_flag && pop_ptr_diff)
     empty_flag <= 'b0;
 end

 assign empty = ~pop_ptr_diff && empty_flag;

 //for output signal full
 assign gray_raddr[ADDRWIDTH-:] = {mem_raddr[ADDRWIDTH-],gray_raddr_temp[ADDRWIDTH-:]};

 always@(*)
   for(i=;i<(ADDRWIDTH-);i=i+)
     gray_raddr_temp[i] = mem_raddr[i] ^ mem_raddr[i+];

 always@(posedge clk_pop or negedge rst_pop_n)
 begin
   if(~rst_pop_n)
     gray_raddr_1r[ADDRWIDTH-:] <=;
   else
     gray_raddr_1r[ADDRWIDTH-:] <= gray_raddr[ADDRWIDTH-:];
 end

 always@(posedge clk_push or negedge rst_push_n)
 begin
   if(~rst_push_n)begin
     gray_raddr_2r_1_sync[ADDRWIDTH-:]<=;
     gray_raddr_3r_2_sync[ADDRWIDTH-:]<=;
   end
   else begin
     gray_raddr_2r_1_sync[ADDRWIDTH-:] <= gray_raddr_1r[ADDRWIDTH-:]:
     gray_raddr_3r_2_sync[ADDRWIDTH-:] <= gray_raddr_2r_sync[ADDRWIDTH-:];
   end
 end

 always@(*)
   biny_raddr[ADDRWIDTH-] = gray_raddr_3r_2_sync[ADDRWIDTH-];
 always@(*)
    for(i=;i<(ADDRWIDTH-);i=i+)
      biny_raddr[ADDRWIDTH--i] = gray_raddr_3r_2_sync[ADDRWIDTH--i] ^biny_raddr_temp[ADDRWIDTH--i];

 always@(*)
   biny_raddr_temp[ADDRWIDTH-:] = biny_raddr[ADDRWIDTH-:];

 assign push_one_left = (biny_raddr[ADDRWIDTH-:] ==(mem_waddr[ADDRWIDTH-:] + 'b1));
 assign push_ptr_diff = (biny_raddr[ADDRWIDTH-:] !=(mem_waddr[ADDRWIDTH-:]));

 always@(posedge clk_push or negedge rst_push_n)
 begin
   if(~rst_push_n)
     full_flag <= 'b0;
   else if(push_one_left && push)
     full_flag <= 'b1;
   else if(full_flag && push_ptr_diff)
     full_flag <='b0
 end

 assign full= ~push_ptr_diff && full_flag;
 assign almost_full = push_one_left;

 endmodule