FPGA输出时钟jitter

If customer performs simple clock forwarding from clock source -> FPGA clock input -> FPGA clock output; what will be jitter specification of such clock output?
I am aware if its MMCM, then we have jitter specifications specified in Clock wiz.
But in this case there is no clock element is used in FPGA its simple clock forwarding.

Answer：

There is no such specification. It would not be practical.
The jitter will depend on their design, the board, the pdn design. Even if they had a MMCM in the clock path that would only be the jitter at the MMCM output not the FPGA output.
We do recommend when forwarding a clock to use an ODDR with the D ports tied to 1 & 0.