memory bist lib

 model NVIC_REG6T_1024x32(resetb,margin,clk,en,we,addr,d,q)
 (
      bist_definition(
            clock     clk    high;
            chip_enable   en    low;
            write_enable   we   high;
            data_in      d(array=:;);
            data_out    q(array=:;);
            address      addr(array=:;);

           dont_touch  margin(array=:;)high;
           dont_touch   resetb low;

           tech = smic11;
           vendor = mentor;
           version="1.0";
           message= "synchrous single port sram";

           address_size = ;
           min_address = ;
           max_address = ;

           read_write_port(
                read_cycle(
                    change addr;
                    wait;
                    wait;
                    expect q;
                    wait;
                 )
                write_cycle(
                     change addr;
                     change d;
                     wait ;
                     assert we;
                     wait;
                     wait;
                   )

            )

       )

 )

写model中，write/read timing 紧凑，很重要，比较难。有的memory model 含有sw(subword) write enable项，tessent工具可以很好的支持，另外UDA可以实现sw部分为0/1。

以上是SRAM 的model，下面是ROM 的model 模板

 model NVIC_ROM_1024x32(resetb,margin,clk,en,addr,q)
 (
     bist_definition(
             clock  clk  high ;
             chip_enable en low;
             data_out      q(array=:;);
             address    addr(array=:;);

              dont_touch       margin high;
              dont_touch       resetb  low;

              tech = smic11;
              vendor = mentor;
              version = "1.0";
              message = "synchronous single port sram";

              address_size = ;
              min_address = ;
              max_address = ;
              data_size = ;

               read_port(
                    read_cycle(
                        change addr;
                        wait;
                        expect q;
                        wait;
                     )
                )

       )

 )