定时延时设计FPGA

以50MHZ时钟为例，进行1秒钟延时，并输出延时使能信号。

首先计算需要多少次计时，MHZ=10的六次方HZ。T=20ns

一秒钟需要计时次数为5的七次方即5000_0000。

然后计算需要几位的寄存器，需要二进制计算器。需要26位寄存器。

//---------方法一（我的写法）-----------------------------------------------
//--------------4999_9999+1=5000_0000----------------------------
reg [:] cnt_1s; //需要26位寄存器来放置4999_9999
    always @ (posedge clk or negedge rst_n)
    begin
    if(!rst_n)
        cnt_1s <= 'd0;
    else if(cnt_1s < 'd4999_9999) //需要减一
        cnt_1s <= cnt_1s + 'b1;
    else
        cnt_1s <= cnt_1s;
end
wire cnt_done1s = (cnt_1s == 'd4999_9999);
//---------需要加上使能信号的方法----------------------------------
reg [:] cnt_1s; //需要26位寄存器来放置4999_9999
    always @ (posedge clk or negedge rst_n)
    begin
    if(!rst_n)
        cnt_1s <= 'd0;
else if (delay_en)     //外界使能信号输入，启动计时
             begin
            if(cnt_1s < 'd4999_9999)
              cnt_1s <= cnt_1s + 'b1;
        else
        cnt_1s <= cnt_1s;
             end
end
wire cnt_done1s = (cnt_1s == 'd4999_9999);

//---------方法二------------------------------------------------
wire cnt_done1s;
reg [:] cnt_1s;
    always @ (posedge clk or negedge rst_n)
    begin
    if(!rst_n)
        cnt_1s <= 'd0;
    else if(cnt_1s < 'd4999_9999)
        cnt_1s <= cnt_1s + 'b1;
    else
        cnt_1s <= cnt_1s;
end
assign cnt_done1s = (cnt_1s == 'd4999_9999);
//------------方法三--------------------------------------
Parameter t_one = 4999_9999;     //需要减一
reg[:] delay_cnt;
always @(posedge clk or negedge rst_n)
    if(!rst_n)
      delay_cnt <= 'd0;
      if(delay_cnt == t_one)
        delay_cnt <= 'd0;
      else
        delay_cnt <= delay_cnt +'b1;
wire delay_done = (delay_cnt == t_one)