更改高通xbl串口log波特率

本修改基于高通QCM6125平台，目的是为了满足客户无聊的需求。

注意事项：

1. 基准时钟频率需要是硬件和驱动支持的频率，时钟频率和分频系数可以从AP侧驱动中找到
2. 最低分频系数需要满足分频公式（能够被整除），分频公式中除以32还是16需要从AP侧驱动中推测过来，或者通过默认的115200波特率的分频系数中推导
3. 6125平台的修改难点是需要自己增加QUPv3控制器设置时钟的相关实现，这个可以从其他QUPv3的高通平台代码中找到，默认是没有的！（这个坑让我填了整整3天）

diff --git a/boot_images/QcomPkg/Library/UartQupv3Lib/UartXBL.c b/boot_images/QcomPkg/Library/UartQupv3Lib/UartXBL.c
index 7e14b69..7ac5b37 100755
--- a/boot_images/QcomPkg/Library/UartQupv3Lib/UartXBL.c
+++ b/boot_images/QcomPkg/Library/UartQupv3Lib/UartXBL.c
@@ -76,12 +76,16 @@ static UINT8 ring_buffer[RING_SIZE]; // size must be a power of 2
static UINT32 read_index = 0; // must be masked before subscripting
static UINT32 write_index = 0; // must be masked before subscripting
static UINT32 tx_fifo_size = 0; // will be populated in register_init
+static UINT32 clk_reg_value = 0; // used to put correct clock divider value based on QUP version
static uart_handle uart_debug_handle;

static const CLOCK_SETTINGS baud_table[] =
{
// bit_rate, input_freq, divider
{ 115200, 7372800, 64 },
+ { 460800, 14745600, 32 },
+ { 921600, 29491200, 32 },
+ { 1000000, 32000000, 32 },
{0}
};

@@ -159,6 +163,8 @@ static uart_result clock_enable(uart_context* uart_ctxt)
return UART_ERROR;
}

+ clk_reg_value = ((divider/32) << 0x4) | 0x1;
+
return UART_SUCCESS;
}

@@ -423,9 +429,9 @@ void register_init(uart_context* uart_ctxt)
REG_OUT(base + GENI4_DATA, GENI_RX_RFR_WATERMARK_REG, temp - 4);

- REG_OUT(base + GENI4_CFG, GENI_SER_M_CLK_CFG, 0x21);
+ REG_OUT(base + GENI4_CFG, GENI_SER_M_CLK_CFG, clk_reg_value);

- REG_OUT(base + GENI4_CFG, GENI_SER_S_CLK_CFG, 0x21);
+ REG_OUT(base + GENI4_CFG, GENI_SER_S_CLK_CFG, clk_reg_value);

//REG_OUT(base + GENI4_IMAGE_REGS, UART_LOOPBACK_CFG, 0x3);

@@ -804,6 +810,8 @@ uart_initialize(void)
uart_open_config c;

c.baud_rate = 115200;
+ // c.baud_rate = 460800;
+ // c.baud_rate = 921600;
c.parity_mode = UART_NO_PARITY;
c.num_stop_bits = UART_1_0_STOP_BITS;
c.bits_per_char = UART_8_BITS_PER_CHAR;