小梅哥课程学习——LED花式玩法（从计数器器到线性序列机）——实验六

//每隔10ms,让led灯的一个8状态循环执行一次（每个变化时间值小一点，方便测试比如设置为10us）
源代码
module counter_led_6(
    clk,
    reset_n,
    Time,
    ctrl,
    led
);
    input clk;
    input reset_n;
    input [31:0] Time;
    input [7:0] ctrl;
    output reg led;
    reg [31:0] counter;
    reg EN;
    //10ms定时器
    reg [18:0] counter0;
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        counter0<=0;
    else if(counter0==500000-1)
        counter0<=0;
    else
        counter0<=counter0+1'b1;
    
    //产生EN
    
   
    always@(posedge clk or negedge reset_n)
    if(!reset_n)
        EN<=0;
    else if(counter0==0)
        EN<=1;
    else if((counter2==7)&&(counter==Time-1))
        EN<=0;
    
    //输入时间间隔
    always@(posedge clk or negedge reset_n)
        if(!reset_n)
            counter<=0;
        else if(EN)begin
            if(counter==Time-1)
                counter<=0;
            else
                counter<=counter+1'b1;
        end
        else
            counter<=0;
    reg [2:0] counter2;
    always@(posedge clk or negedge reset_n)
        if(!reset_n)
            counter2<=0;
        else if(EN)begin
            if(counter==Time-1)
                counter2<=counter2+1'b1;
        end
        else
            counter2<=0;
     
    always@(posedge clk or negedge reset_n)
        if(!reset_n)
            led<=0;
        else case(counter2)
            0:led<=ctrl[0];
            1:led<=ctrl[1];
            2:led<=ctrl[2];
            3:led<=ctrl[3];
            4:led<=ctrl[4];
            5:led<=ctrl[5];
            6:led<=ctrl[6];
            7:led<=ctrl[7];
            default led<=led;
        endcase
endmodule
仿真代码
`timescale 1ns/1ns
module counter_led_6_tb();
    reg clk;
    reg reset_n;
    reg [31:0] Time;
    reg [7:0] ctrl;
    wire led;
    
    counter_led_6 counter_led_6_inst0(
    .clk(clk),
    .reset_n(reset_n),
    .ctrl(ctrl),
    .Time(Time),
    .led(led)
    );
    initial clk=1;
    always #10 clk=!clk;
    
    initial begin
        reset_n=0;
        ctrl=0;
        Time=0;
        
        #201;
        reset_n=1;
        #2000;
        Time=2500;
        ctrl=8'b1000_0110;
        
        
        #2000000000;
        $stop;
    end

endmodule