Virtual Memory PAGE TABLE STRUCTURE

COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION

The basic mechanism for reading a word from memory
involves the translation of a virtual, or logical, address, consisting of page number
and offset, into a physical address, consisting of frame number and offset, using a
page table. Because the page table is of variable length, depending on the size of the
process, we cannot expect to hold it in registers. Instead, it must be in main memory
to be accessed. Figure 8.16 suggests a hardware implementation of this scheme.
When a particular process is running, a register holds the starting address of the
page table for that process. The page number of a virtual address is used to index
that table and look up the corresponding frame number. This is combined with the
offset portion of the virtual address to produce the desired real address.

In most systems, there is one page table per process. But each process can
occupy huge amounts of virtual memory. For example, in the VAX architecture,
each process can have up to 2
31
= 2 Gbytes of virtual memory. Using 2
9
= 512@byte
pages, that means that as many as 2
22
page table entries are required per process.
Clearly, the amount of memory devoted to page tables alone could be unacceptably
high. To overcome this problem, most virtual memory schemes store page tables in
virtual memory rather than real memory. This means that page tables are subject to
paging just as other pages are. When a process is running, at least a part of its page
table must be in main memory, including the page table entry of the currently execut-
ing page. Some processors make use of a two-level scheme to organize large page
tables. In this scheme, there is a page directory, in which each entry points to a page
table. Thus, if the length of the page directory is X, and if the maximum length of a
page table is Y, then a process can consist of up to X
*
Y pages. Typically, the maxi-
mum length of a page table is restricted to be equal to one page. We will see an exam-
ple of this two-level approach when we consider the Pentium II later in this chapter.

An alternative approach to the use of one- or two-level page tables is the use
of an inverted page table structure (Figure 8.17). Variations on this approach are
used on the Power PC, Ultra SPARC, and the IA-64 architecture. An implementa-
tion of the Mach OS on the RT-PC also uses this technique.

In this approach, the page number portion of a virtual address is mapped into
a hash value using a simple hashing function.
2
The hash value is a pointer to the
inverted page table, which contains the page table entries. There is one entry in the

2

A hash function maps numbers in the range 0 through M into numbers in the range 0 through N, where
M > N . The output of the hash function is used as an index into the hash table. Since more than one input
maps into the same output, it is possible for an input item to map to a hash table entry that is already
occupied. In that case, the new item must overflow into another hash table location. Typically, the new
item is placed in the first succeeding empty space, and a pointer from the original location is provided to
chain the entries together. See Appendix C for more information on hash functions.

inverted page table for each real memory page frame rather than one per virtual
page. Thus a fixed proportion of real memory is required for the tables regardless of
the number of processes or virtual pages supported. Because more than one virtual
address may map into the same hash table entry, a chaining technique is used for
managing the overflow. The hashing technique results in chains that are typically
short—between one and two entries. The page table’s structure is called inverted
because it indexes page table entries by frame number rather than by virtual page
number.