cyclone4驱动LM75A温湿度传感器学习

1. LM75A第一次使用，I2C接口，8脚

2. 打开quartus工程，下面只要是看看代码结构，问题在于多个always语句，逻辑上不太好分清楚，主要看状态机

 module I2C_READ(
        clk,
 rst_n,
 scl,sda,data
               );

 input clk;//总线时钟 50MHz
 input rst_n;//异步复位,低电平有效  

 output scl;//SCL 时钟
 inout  sda;// SDA 数据总线
 output [:] data;//温度数据  

 reg [:]data_r;//温度数据寄存器
 reg scl;//SCL 总线寄存器
 reg sda_r;//SDA 总线寄存器
 reg sda_link;//SDA 总线数据方向标志
 reg [:]scl_cnt;//SCL 时钟产生计数器
 reg [:]cnt;//用来标记SCL时钟计数器
 reg [:]timer_cnt;//定时器,每隔2s 读取一次温度数据
 reg [:]data_cnt;//数据串并转换寄存器
 reg [:]address_reg;//器件地址寄存器
 reg [:]state;//状态寄存器
 //////////////////////////////////////////////////////////////////////////////////
 //进程1、2、3：产生SCL 总线时钟
 always@(posedge clk or negedge rst_n)
     begin
         if(!rst_n)
             scl_cnt <= 'd0;
         else if(scl_cnt == 'd199)
             scl_cnt <= 'd0;
         else
             scl_cnt <= scl_cnt + 'b1;
     end
 always@(posedge clk or negedge rst_n)
     begin
         if(!rst_n)
             cnt <= 'd5;
         else
             case(scl_cnt)
                 'd49: cnt <= 3'd1;//高电平中间
                 'd99: cnt <= 3'd2;//下降沿
                 'd149:cnt <= 3'd3;//低电平中间
                 'd199:cnt <= 3'd0;//上升沿
                default: cnt <= 'd5;
             endcase
     end
 `define SCL_HIG (cnt == 'd1)
 `define SCL_NEG (cnt == 'd2)
 `define SCL_LOW (cnt == 'd3)
 `define SCL_POS (cnt == 'd0)
 always@(posedge clk or negedge rst_n)
     begin
         if(!rst_n)
             scl <= 'b0;
         else if(`SCL_POS)
             scl <= 'b1;
         else if(`SCL_NEG)
             scl <= 'b0;
     end
 //////////////////////////////////////////////////////////////////////////////////
 //进程4：定时器,每隔1s 读取一次温度数据
 always@(posedge clk or negedge rst_n)
     begin
         if(!rst_n)
             timer_cnt <= 'd0;
         else if(timer_cnt == 'd49999999)
             timer_cnt <= 'd0;
         else
             timer_cnt <= timer_cnt + 'b1;
     end
 //////////////////////////////////////////////////////////////////////////////////
 //状态机定义
 parameter IDLE  = 'b0_0000_0000,
              START  = 'b0_0000_0010,
              ADDRESS    = 'b0_0000_0100,
              ACK1       = 'b0_0000_1000,
              READ1  = 'b0_0001_0000,
              ACK2       = 'b0_0010_0000,
              READ2  = 'b0_0100_0000,
              NACK       = 'b0_1000_0000,
              STOP       = 'b1_0000_0000;
 `define DEVICE_ADDRESS 'b1001_0001//器件地址,读操作
 //////////////////////////////////////////////////////////////////////////////////
 //进程5：状态机描述
 always@(posedge clk or negedge rst_n)
     begin
         if(!rst_n)
             begin
                 data_r  <= 'd0;
                 sda_r       <= 'b1;
                 sda_link    <= 'b1;
                 state       <= IDLE;
                 address_reg <= 'd0;
                 data_cnt    <= 'd0;
             end
         else
             case(state)
                 IDLE:
                     begin
                         sda_r   <= 'b1;
                         sda_link <= 'b1;
                         if(timer_cnt == 'd49999999)
                             state <= START;
                         else
                             state <= IDLE;
                     end
                 START://产生起始信号
                     begin
                         if(`SCL_HIG)
                             begin
                                 sda_r       <= 'b0;
                                 sda_link    <= 'b1;
                                 address_reg <= `DEVICE_ADDRESS;
                                 state           <= ADDRESS;
                                 data_cnt        <= 'd0;
                             end
                         else
                             state <= START;
                     end
                 ADDRESS://主机对器件进行寻址
                     begin
                         if(`SCL_LOW)
                             begin
                                 if(data_cnt == 'd8)//寻址完成,SDA改变方向,器件准备输出应答讯号
                                     begin
                                         state   <= ACK1;
                                         data_cnt <=  'd0;
                                         sda_r       <= 'b1;
                                         sda_link    <= 'b0;
                                     end
                                 else//寻址过程中,SDA对器件作为输入
                                     begin
                                         state   <= ADDRESS;
                                         data_cnt <= data_cnt + 'b1;
                                         case(data_cnt)
                                             'd0: sda_r <= address_reg[7];
                                             'd0: sda_r <= address_reg[7];
                                             'd1: sda_r <= address_reg[6];
                                             'd2: sda_r <= address_reg[5];
                                             'd3: sda_r <= address_reg[4];
                                             'd4: sda_r <= address_reg[3];
                                             'd5: sda_r <= address_reg[2];
                                             'd6: sda_r <= address_reg[1];
                                             'd7: sda_r <= address_reg[0];
                                             default: ;
                                         endcase
                                     end
                             end
                         else
                             state <= ADDRESS;
                     end
                 ACK1://器件输出应答信号
                     begin
                         if(!sda && (`SCL_HIG))
                             state <= READ1;
                         else if(`SCL_NEG)
                             state <= READ1;
                         else
                             state <= ACK1;
                     end
                 READ1://读器件数据,高字节
                     begin
                         if((`SCL_LOW) && (data_cnt == 'd8))//读高字节数据完成,SDA改变方向,主机准备输出应答讯号
                             begin
                                 state   <= ACK2;
                                 data_cnt <= 'd0;
                                 sda_r       <= 'b1;
                                 sda_link    <= 'b1;
                             end
                         else if(`SCL_HIG)//读数据过程中,器件作为输出，这里有疑问，不是应该的等SCL一个时钟吗？SCL_HIG
                             begin
                                 data_cnt <= data_cnt + 'b1;
                                 case(data_cnt)
                                     'd0: data_r[15] <= sda;
                                     'd1: data_r[14] <= sda;
                                     'd2: data_r[13] <= sda;
                                     'd3: data_r[12] <= sda;
                                     'd4: data_r[11] <= sda;
                                     'd5: data_r[10] <= sda;
                                     'd6: data_r[9]  <= sda;
                                     'd7: data_r[8]  <= sda;
                                     default: ;
                                 endcase
                             end
                         else
                             state <= READ1;
                     end
                 ACK2://主机输出应答讯号
                     begin
                         if(`SCL_LOW)
                             sda_r <= 'b0;
                         else if(`SCL_NEG)
                             begin
                                 sda_r   <= 'b1;
                                 sda_link    <= 'b0;
                                 state       <= READ2;
                             end
                         else
                             state <= ACK2;
                     end
                 READ2://读低字节数据
                     begin
                         if((`SCL_LOW) && (data_cnt == 'd8))
                             begin
                                 state   <= NACK;
                                 data_cnt <= 'd0;
                                 sda_r       <= 'b1;
                                 sda_link    <= 'b1;
                             end
                         else if(`SCL_HIG)
                             begin
                                 data_cnt <= data_cnt + 'b1;
                                 case(data_cnt)
                                     'd0: data_r[7] <= sda;
                                     'd1: data_r[6] <= sda;
                                     'd2: data_r[5] <= sda;
                                     'd3: data_r[4] <= sda;
                                     'd4: data_r[3] <= sda;
                                     'd5: data_r[2] <= sda;
                                     'd6: data_r[1]  <= sda;
                                     'd7: data_r[0]  <= sda;
                                     default: ;
                                 endcase
                             end
                         else
                             state <= READ2;
                     end
                 NACK://主机非应答
                     begin
                         if(`SCL_LOW)
                             begin
                                 state <= STOP;
                                 sda_r   <= 'b0;
                             end
                         else
                             state <= NACK;
                     end
                 STOP:
                     begin
                         if(`SCL_HIG)
                             begin
                                 state <= IDLE;
                                 sda_r <= 'b1;
                             end
                         else
                             state <= STOP;
                     end
                 default: state <= IDLE;
             endcase
     end
 assign sda   = sda_link ? sda_r: 'bz;
 assign data  = data_r;
 endmodule

3. 这个代码需要好好研究下，有疑问的地方，data_cnt <= data_cnt + 1'b1;每次读一位的时候，SCL应该有一个时钟，按照这个时钟去读的，为啥代码使用data_cnt这个变量，感觉不对啊？这里不是很明白

  begin
                                          state   <= ADDRESS;
                                          data_cnt <= data_cnt + 'b1;
                                          case(data_cnt)
                                              'd0: sda_r <= address_reg[7];
                                              'd0: sda_r <= address_reg[7];
                                              'd1: sda_r <= address_reg[6];
                                              'd2: sda_r <= address_reg[5];
                                              'd3: sda_r <= address_reg[4];
                                              'd4: sda_r <= address_reg[3];
                                              'd5: sda_r <= address_reg[2];
                                              'd6: sda_r <= address_reg[1];
                                              'd7: sda_r <= address_reg[0];
                                              default: ;
                                          endcase
                                      end