(转帖) 如何將值delay n個clock? (SOC) (Verilog)

来源：http://www.cnblogs.com/oomusou/archive/2009/06/15/verilog_dly_n_clk.html

 /*
 (C) OOMusou 2009 http://oomusou.cnblogs.com

 Filename    : delay_3t.v
 Compiler    : NC-Verilog 5.4
 Description : delay 3t method 1
 Release     : 06/15/2009 1.0
 */

 module delay_3t (
   clk,
   rst_n,
   d,
   q
 );

 input  clk;
 input  rst_n;
 input  d;
 output q;

 reg d_dly_1t;
 reg d_dly_2t;
 reg d_dly_3t;

 assign q = d_dly_3t;

 always@(posedge clk or negedge rst_n) begin
   if (!rst_n) begin
     d_dly_1t <= ;
     d_dly_2t <= ;
     d_dly_3t <= ;
   end
   else begin
     d_dly_1t <= d;
     d_dly_2t <= d_dly_1t;
     d_dly_3t <= d_dly_2t;
   end
 end

 endmodule

 /*
 (C) OOMusou 2009 http://oomusou.cnblogs.com

 Filename    : delay_3t.v
 Compiler    : NC-Verilog 5.4
 Description : delay 3t method 2
 Release     : 06/15/2009 1.0
 */

 module delay_3t (
   clk,
   rst_n,
   d,
   q
 );

 input  clk;
 input  rst_n;
 input  d;
 output q;

 reg d_dly_1t;
 reg d_dly_2t;
 reg d_dly_3t;

 assign q = d_dly_3t;

 always@(posedge clk or negedge rst_n) begin
   if (!rst_n)
     {d_dly_3t, d_dly_2t, d_dly_1t}  <= ;
   else
     {d_dly_3t, d_dly_2t, d_dly_1t} <= {d_dly_2t, d_dly_1t, d};
 end

 endmodule

 /*
 (C) OOMusou 2009 http://oomusou.cnblogs.com

 Filename    : delay_nt.v
 Compiler    : NC-Verilog 5.4
 Description : delay 3t method 3
 Release     : 06/15/2009 1.0
 */

 module delay_nt (
   clk,
   rst_n,
   d,
   q
 );

 parameter n = ;

 input  clk;
 input  rst_n;
 input  d;
 output q;

 reg [n-:] r;

 assign q = r[n-];

 integer i;

 always@(posedge clk or negedge rst_n) begin
   if (!rst_n)
     r <= ;
   else begin
     for(i=; i<n-; i=i+)
       r[i+] <= r[i];

     r[] <= d;
   end
 end

 endmodule

 /*
 (C) OOMusou 2009 http://oomusou.cnblogs.com

 Filename    : delay_nt.v
 Compiler    : NC-Verilog 5.4
 Description : delay 3t method 4
 Release     : 06/15/2009 1.0
 */

 module delay_nt (
   clk,
   rst_n,
   d,
   q
 );

 parameter n = ;

 input  clk;
 input  rst_n;
 input  d;
 output q;

 reg [n-:] r;

 assign q = r[n-];

 always@(posedge clk or negedge rst_n) begin
   if (!rst_n)
     r <= ;
   else
     r <= {r, d};
 end

 endmodule

{}写法是Verilog的独门绝技，这样就不再需要for，这也是为什么Verilog宁愿从C语言抢走{}换来begin, end，因为{}这种合并的写法非常的好用。Testbench与模拟波型图也与Method 1与Method 2一样，再次省略。这种写法使用了parameter，无论要delay几个clk，只需修改n即可，而且与Quartus II优化后的硬件一样，我们再次将编译过的RTL Viewer打开做验证。

Conclusion
这4种写法最后合出来的硬件都一样，表示现在的合成器都够聪明，差别只是在哪种coding style较好，将来比较好维护。另外也是开开眼界，若将来阅读其他人的code，马上就知道对方想表达的意思。