基于Verilog的按键检测实验

一、模块框图及基本思路

detect_module:检测按键输入脚的电平边沿变化

delay_10ms_module:延时消抖，输出按键有效信号

debounce_module:前两个模块的组合模块

key_control:按键信号控制Led

key_demo:顶层模块

二、软件部分

detect_module.v

 module detect_module(
     CLK,RSTn,
     Key_Pin_In,
     H2L_Sig,L2H_Sig
     );
     input CLK,RSTn;
     input Key_Pin_In;
     output H2L_Sig,L2H_Sig;

     /****************************************************/
     localparam T100us=50_000_000/1_000_000*-;
     reg [:] Count_100us;
     reg isEn;

     always @(posedge CLK or negedge RSTn)
     begin
         if(!RSTn)
         begin
             Count_100us<='d0;
             isEn<='b0;
         end
         else if(Count_100us==T100us)
             isEn<='b1;
         else Count_100us<=Count_100us+'b1;
     end

     /****************************************************/
     reg H2L_Sig_r1,H2L_Sig_r2;
     reg L2H_Sig_r1,L2H_Sig_r2;
     always @(posedge CLK or negedge RSTn)
     begin
         if(!RSTn)
         begin
             H2L_Sig_r1<='b1;
             H2L_Sig_r2<='b1;
             L2H_Sig_r1<='b0;
             L2H_Sig_r2<='b0;
         end
         else
         begin
             H2L_Sig_r1<=Key_Pin_In;
             H2L_Sig_r2<=H2L_Sig_r1;
             L2H_Sig_r1<=Key_Pin_In;
             L2H_Sig_r2<=L2H_Sig_r1;
         end
     end

     /****************************************************/

     assign H2L_Sig=isEn?(H2L_Sig_

delay_10ms_module.v

 module delay10ms_module(
     CLK,RSTn,
     H2L_Sig,L2H_Sig,
     Key_Sig_Out
     );
      input CLK,RSTn;
      input H2L_Sig,L2H_Sig;
      output Key_Sig_Out;

      /**********************************************/
      localparam T10ms=50_000_000/*-;
      reg[:] Count_10ms;
      reg isCount;
      always @(posedge CLK or negedge RSTn)
      begin
         if(!RSTn)
         begin
             Count_10ms<='d0;
         end
         else if(Count_10ms==T10ms) Count_10ms<='d0;
         else if(isCount) Count_10ms<=Count_10ms+'b1;
      end

      /**********************************************/
      reg Key_Sig_Out_r;
      reg [:]i;
      always @(posedge CLK or negedge RSTn)
      begin
         if(!RSTn)
         begin
             Key_Sig_Out_r<=;
             i<=;
             isCount<='b0;
         end
         else
             case(i)
                 'd0:if(H2L_Sig) i<=2'd1;
                         else if(L2H_Sig) i<='d2;
                 'd1:if(Count_10ms==T10ms) begin Key_Sig_Out_r<=1'b1;isCount<='b0;i<=2'd0;end
                         else isCount<='b1;
                 'd2:if(Count_10ms==T10ms) begin Key_Sig_Out_r<=1'b0;isCount<='b0;i<=2'd0;end
                         else isCount<='b1;

             endcase
      end
      /***************************************************/
     assign Key_Sig_Out=Key_Sig_Out_r;

 endmodule

debounce_module.v

 module debounce_module(
     CLK,RSTn,
     Key_Pin_In,
     Key_Sig_Out
     );
      input CLK,RSTn;
      input Key_Pin_In;
      output Key_Sig_Out;

     wire H2L_Sig;
     wire L2H_Sig;

     detect_module U0(
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Pin_In(Key_Pin_In),
         .H2L_Sig(H2L_Sig),
         .L2H_Sig(L2H_Sig)
     );
     delay10ms_module U1(
         .CLK(CLK),
         .RSTn(RSTn),
         .H2L_Sig(H2L_Sig),
         .L2H_Sig(L2H_Sig),
         .Key_Sig_Out(Key_Sig_Out)
     );

 endmodule

key_control.v

 module key_control(
     CLK,RSTn,
     Key_Sig,
     Led
     );
      input CLK,RSTn;
      input Key_Sig;
      output Led;

      /***********************************/
      reg Key_Sig_r1,Key_Sig_r2;
      wire Led_Sig;
      always @(posedge CLK or negedge RSTn)
      begin
         if(!RSTn)
         begin
             Key_Sig_r1<='b0;
             Key_Sig_r2<='b0;
         end
         else
         begin
             Key_Sig_r1<=Key_Sig;
             Key_Sig_r2<=Key_Sig_r1;
         end
      end
      assign Led_Sig=Key_Sig_r1&!Key_Sig_r2;
      /************************************/
      reg rLed;
      always @(posedge CLK or negedge RSTn )
      begin
          if(!RSTn) rLed<='b0;
          else if(Led_Sig) rLed<=~rLed;
      end
     assign Led=rLed;
 endmodule

key_demo.v

 module key_demo(
     CLK,RSTn,
     Key_Pin_In,Led
     );
      input CLK,RSTn;
      input [:]Key_Pin_In;
      output [:]Led;

     wire Key_Sig1;
     key_control U0 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Sig(Key_Sig1),
         .Led(Led[])
     );
     debounce_module U1 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Pin_In(Key_Pin_In[]),
         .Key_Sig_Out(Key_Sig1)
     );

     wire Key_Sig2;
     key_control U2 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Sig(Key_Sig2),
         .Led(Led[])
     );
     debounce_module U3 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Pin_In(Key_Pin_In[]),
         .Key_Sig_Out(Key_Sig2)
     );

    wire Key_Sig3;
     key_control U4 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Sig(Key_Sig3),
         .Led(Led[])
     );
     debounce_module U5 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Pin_In(Key_Pin_In[]),
         .Key_Sig_Out(Key_Sig3)
     );

     wire Key_Sig4;
     key_control U6 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Sig(Key_Sig4),
         .Led(Led[])
     );
     debounce_module U7 (
         .CLK(CLK),
         .RSTn(RSTn),
         .Key_Pin_In(Key_Pin_In[]),
         .Key_Sig_Out(Key_Sig4)
     );

 endmodule

三、硬件部分

黑金SPARTAN-6开发板

 NET "CLK" LOC = T8;
 NET "RSTn" LOC = L3;

 NET "Led[0]" LOC = P4;
 NET "Led[1]" LOC = N5;
 NET "Led[2]" LOC = P5;
 NET "Led[3]" LOC = M6;

 NET "Key_Pin_In[0]" LOC = C3;
 NET "Key_Pin_In[1]" LOC = D3;
 NET "Key_Pin_In[2]" LOC = E4;
 NET "Key_Pin_In[3]" LOC = E3;