9.3.2 The force and release procedural statements

Frm： IEEE Std 1364™-2001, IEEE Standard Verilog® Hardware Description Language

Another form of procedural continuous assignment is provided by the force and release procedural statements. These statements have a similar effect to the assign-deassign pair, but a force can be applied to nets as well as to variables. The left-hand side of the assignment can be a variable, a net, a constant bit-select of a vector net, a part-select of a vector net, or a concatenation. It cannot be a memory word (array reference) or a bit-select or a part-select of a vector variable.

A force statement to a variable shall override a procedural assignment or procedural continuous assignment that takes place on the variable until a release procedural statement is executed on the variable. After the release procedural statement is executed, the variable shall not immediately change value (as would a net that is assigned with a procedural continuous assignment). The value specified in the force statement shall be maintained in the variable until the next procedural assignment takes place, except in the case where a procedural continuous assignment is active on the variable.

A force procedural statement on a net overrides all drivers of the net—gate outputs, module outputs, and continuous assignments—until a release procedural statement is executed on the net.

Releasing a variable that currently has an active procedural continuous assignment shall re-establish that assignment.

Example:

module test;
reg a, b, c, d;
wire e;
and and1 (e, a, b, c);
initial begin
$monitor("%d d=%b,e=%b", $stime, d, e);
assign d = a & b & c;
a = ;
b = ;
c = ;
#;
force d = (a | b | c);
force e = (a | b | c);
# $stop;
release d;
release e;
# $finish;
end
endmodule
Results:
 d=,e=
 d=,e=
 d=,e=

In this example, an and gate instance and1 is “patched” as an or gate by a force procedural statement that forces its output to the value of its logical or inputs, and an assign procedural statement of logical and values is “patched” as an assign procedural statement of logical or values.

The right-hand side of a procedural continuous assignment or a force statement can be an expression. This shall be treated just as a continuous assignment; that is, if any variable on the right-hand side of the assignment changes, the assignment shall be re-evaluated while the assign or force is in effect. For example:

force a = b + f(c) ;

Here, if b changes or c changes, a will be forced to the new value of the expression b+f(c).