verilog 常见单元描述

半加器：

//行为级建模
module half_adder2(a, b, sum, c_out);
    input a, b;
    output sum, c_out;
    assign {c_out, sum} = a + b;
endmodule

// 结构级建模
module half_adder(a, b, sum, c_out);
    input a, b;
    output sum, c_out;
    xor (sum, a, b);
    and (c_out, a, b);
endmodule

进位选择加法器：

多路复用器：

//行为模型
module Mux_4_32_case(
    output        [:]        mux_out,
    input         [:]        data_3, data_2, data_1, data_0,
                  [:]         select,
    input                       enabel
);
    reg           [:]        mux_int;
    assign mux_out = enable ? mux_int : 32b'z;
    always @ (data_3, data_2, data_1, data_0, select)
        case (select)
            :                   mux_int = data_0;
            :                   mux_int = data_1;
            :                   mux_int = data_2;
            :                   mux_int = data_3;
            default:             mux_int = 32b'x;　　　　//当select包含z or x时的状态，不加default vivado综合出来的电路图没有区别，但是不知道在tb上会不会出问题
        endcase
endmodule

//使用if条件语句行为级建模
module Mux_4_32_if(
    output      [:]      mux_out,
    input       [:]      data_3, data_2, data_1, data_0,
    input       [:]       select,
    input                   enable
);
    reg         [:]      mux_int;
    assign      mux_out = enable ? mux_int : 'bz;
    always @(data_3, data_2, data_1, data_0, select)
        if(select == 'b00) mux_int = data_0;   else
            if(select == 'b01) mux_int = data_1;   else
                if(select == 'b10) mux_int = data_2;   else
                    if(select == 'b11) mux_int = data_3;    else
                        mux_int = 'bx;
endmodule

module Mux_4_32_CA(
    output      [:]      mux_out,
    input       [:]      data_3, data_2, data_1, data_0,
    input       [:]       select,
    input                   enable
);
    wire        [:]      mux_int;
    assign      mux_out = enable ? mux_int : 'bz;
    assign      mux_int = (select==) ? data_0:
                             (select==) ? data_1:
                                (select==) ? data_2:
                                   (select==) ? data_3: 'bx;
endmodule

编码器

//case 优先编码器
module priority_case(
    output  reg [:]   Code,
    output              valid_data,
    input       [:]   Data
    );
　　 assign　　valid_data = |Data;　　//“reduction or" operator
    always  @(Data)
        casex   (Data)
            'b1xxxxxxx     :   Code = 7;
            'b01xxxxxx     :   Code = 6;
            'b001xxxxx     :   Code = 5;
            'b0001xxxx     :   Code = 4;
            'b00001xxx     :   Code = 3;
            'b000001xx     :   Code = 2;
            'b0000001x     :   Code = 1;
            'b00000001     :   Code = 0;
            default         :   Code = 'bx;
        endcase
endmodul