Why use MSIX message signal interrupt

　　处理一个低版本内核中断向量表不够问题：__assign_irq_vector 关联irq 和 vector失败问题； （bug还没解决先记录一下吧）

　　同时先学习一下MSI-X：MSI， message signal interrupt, 是PCI设备通过写一个特定消息到特定地址，从而触发一个CPU中断。

什么是MSI-X中断?

MSI， message signal interrupt, 是PCI设备通过写一个特定消息到特定地址，从而触发一个CPU中断。特定消息指的是PCIe总线中的Memory Write TLP, 特定地址一般存放在MSI capability中。

MSI-x是MSI的扩展和增强。MSI有它自身的局限性，MSI最多支持32个中断，且要求中断向量连续， 而MSI-x没有这个限制，且支持的中断数量更多。此外，MSI-X的中断向量信息并不直接存储在capability中，而是在一块特殊Memory中.

　Pin-based PCI interrupts are often shared amongst several devices. To support this, the kernel must call each interrupt handler associated with an interrupt, which leads to reduced performance for the system as a whole. MSIs are never shared, so this problem cannot arise.

　　When a device writes data to memory, then raises a pin-based interrupt, it is possible that the interrupt may arrive before all the data has arrived in memory (this becomes more likely with devices behind PCI-PCI bridges). In order to ensure that all the data has arrived in memory, the interrupt handler must read a register on the device which raised the interrupt. PCI transaction ordering rules require that all the data arrive in memory before the value may be returned from the register. Using MSIs avoids this problem as the interrupt-generating write cannot pass the data writes, so by the time the interrupt is raised, the driver knows that all the data has arrived in memory.

　　PCI devices can only support a single pin-based interrupt per function. Often drivers have to query the device to find out what event has occurred, slowing down interrupt handling for the common case. With MSIs, a device can support more interrupts, allowing each interrupt to be specialised to a different purpose. One possible design gives infrequent conditions (such as errors) their own interrupt which allows the driver to handle the normal interrupt handling path more efficiently. Other possible designs include giving one interrupt to each packet queue in a network card or each port in a storage controller　

也就是说和传统的INTx中断相比，MSI中断有以下几个优点:
(1) 基于引脚的传统中断会被多个设备所共享，中断共享时，如果触发了中断，linux需要一一调用对应的中断处理函数，这样会有性能上的损失，而MSI不存在共享的问题。
(2) 设备向内存写入数据，然后发起引脚中断， 有可能会出现CPU收到中断时，数据还没有达到内存。 而使用MSI中断时，产生中断的写不能越过数据的写，驱动可以确信所有的数据已经达到内存。
(3) 多功能的PCI设备，每一个功能最多只有一个中断引脚，当具体的事件产生时，驱动需要查询设备才能知道是哪一个事件产生，这样会降低中断的处理速度。而一个设备可以支持32个MSI中断，每个中断可以对应特定的功能。

• PCIe设备在提交MSI中断请求时，都是向MSI/MSI-X Capability结构中的Message Address的地址写Message Data数据，从而组成一个存储器写TLP，向处理器提交中断请求

参考：https://www.kernel.org/doc/html/latest/PCI/index.html