Verilog三线 - 八线译码器

参阅了一些书籍和网上的写法，在此Mark。

布尔表达式法

 module decode3_8_assign (data_in,data_out,enable);//算法实现
     input [:] data_in;
     input enable;
     output [:] data_out;
     reg data_a = 'b00000001;
     assign data_out = (enable)?(~(data_a << data_in)):'b11111111;
 endmodule

testbench:

 `timescale  ns/  ps
 module decode3_8_assign_vlg_tst();
     reg [:] data_in;
     reg enable;
     wire [:] data_out;
     decode3_8_assign i1 (
         .data_in(data_in),
         .data_out(data_out),
         .enable(enable)
     );
     initial
     begin
         enable = ;
         data_in = ;
         # enable  = ;
         # data_in = ;
         # data_in = ;
         # data_in = ;
         # data_in = ;
         # data_in = ;
         # data_in = ;
         # data_in = ;
         # data_in = ;
     end
 endmodule

case语句法

 module decode3_8_case (data_in,data_out,enable);
     input [:] data_in;
     input enable;
     output [:] data_out;
     reg [:] data_out;
     always @ (data_in or enable)
         begin
             if (enable)
                 case (data_in)
                     'b000 : data_out = 8'b11111110;
                     'b001 : data_out = 8'b11111101;
                     'b010 : data_out = 8'b11111011;
                     'b011 : data_out = 8'b11110111;
                     'b100 : data_out = 8'b11101111;
                     'b101 : data_out = 8'b11011111;
                     'b110 : data_out = 8'b10111111;
                     'b111 : data_out = 8'b01111111;
                     default : data_out = 'bxxxxxxxx;
                 endcase
             else data_out = 'b11111111;
         end
 endmodule

testbench：

 `timescale  ps/  ps
 module decode3_8_case_vlg_tst();
     reg [:] data_in;
     reg enable;
     wire [:] data_out;
     decode3_8_case i1 (
         .data_in(data_in),
         .data_out(data_out),
         .enable(enable)
     );
     initial
         begin
             data_in = ;
             enable = ;
             # enable = ;
             while (data_in <= 'b111)//for (i = 0;i <= 3'b111;i = i + )
                 begin
                     # data_in = data_in + ;
                 end
         # $stop;
         end
 endmodule

for语句法

 module decode3_8_for (data_out,data_in,enable);
     input [:] data_in;
     input enable;
     output [:] data_out;
     reg [:] data_out;
     integer i;
     always @ (data_in or enable)
         begin
             if (enable)
                 begin
                     for (i = ;i < ;i = i + )
                         begin
                             if (data_in == i)
                                 data_out[i] = ;
                             else
                                 data_out[i] = ;
                         end
                 end
             else
                 data_out = 'hff;
         end
 endmodule

testbench：

 `timescale  ps/  ps
 module decode3_8_for_vlg_tst();
     reg [:] data_in;
     reg enable;
     wire [:] data_out;
     decode3_8_for i1 (
         .data_in(data_in),
         .data_out(data_out),
         .enable(enable)
     );
     initial
         begin
             data_in = ;
             enable = ;
             # enable = ;
             while (data_in <= 'b111)//for (i = 0;i <= 3'b111;i = i + )
                 begin
                     # data_in = data_in + ;
                 end
             # $stop;
         end
 endmodule

if语句法

 `timescale  ps/  ps
 module decode3_8_for_vlg_tst();
     reg [:] data_in;
     reg enable;
     wire [:] data_out;
     decode3_8_for i1 (
         .data_in(data_in),
         .data_out(data_out),
         .enable(enable)
     );
     initial
         begin
             data_in = ;
             enable = ;
             # enable = ;
             while (data_in <= 'b111)//for (i = 0;i <= 3'b111;i = i + )
                 begin
                     # data_in = data_in + ;
                 end
             # $stop;
         end
 endmodule

testbench：

 `timescale  ns/  ps
 module decode3_8_if_vlg_tst();
     reg [:] data_in;
     reg enable;
     wire [:] data_out;
     integer i;
     decode3_8_if i1 (
         .data_in(data_in),
         .data_out(data_out),
         .enable(enable)
     );
     initial
     begin
         data_in = ;
         enable = ;
         # enable = ;
         for (i = ;i < ;i = i + )
             begin
                 # data_in = data_in + ;
             end
     end
 endmodule

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