Verilog HDL小练习

5s内15Hz4个LED闪烁，再两秒熄灭，循环往复。

引入en，可以使得4个LED灯全亮，以及恢复周期变化。

module led(clk_27MHZ, en, led1, led2, led3, led4);

input clk_27MHZ, en;
output reg led1, led2, led3, led4;
reg[25:0] counter_15HZ;
reg[25:0] counter_1HZ;
reg[3:0]  count_5s, count_7s;
reg		  clk_15HZ;
reg		  clk_1HZ;

always@(posedge clk_27MHZ) begin
	if(counter_15HZ <= 899999) begin
		counter_15HZ <= counter_15HZ+1;
	end
	else begin
		counter_15HZ <= 0;
		clk_15HZ <= ~clk_15HZ;
	end

	if(counter_1HZ <= 13499999) begin
		counter_1HZ <= counter_1HZ+1;
	end
	else begin
		counter_1HZ <= 0;
		clk_1HZ <= ~clk_1HZ;
	end
end

always@(posedge clk_1HZ, posedge en) begin
	if(en) begin
		{led1, led2, led3, led4} <= 'b1111;
	end
	else begin
			if(count_5s <= 4) begin
				count_5s <= count_5s+1;
				count_7s <= count_7s+1;
				if(clk_15HZ) begin
					{led1, led2, led3, led4} <= 'b1111;
				end
				else begin
					{led1, led2, led3, led4} <= 'b0000;
				end
			end
			else begin
				count_7s <= count_7s+1;
				{led1, led2, led3, led4} <= 'b0000;
				if(count_7s == 6) begin
					count_7s <= 0;
					count_5s <= 0;
				end
			end
	end
end
endmodule