FIFO

FIFO存储器 FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单，但缺点就是只能顺序写入数据，顺序的读出数据，其数据地址由内部读写指针自动加1完成，不能像普通存储器那样可以由地址线决定读取或写入某个指定的地址。  在系统设计中，以增加数据传输率、处理大量数据流、匹配具有不同传输率的系统为目的而广泛使用FIFO存储器，从而提高了系统性能.

FIFO参数：

FIFO的宽度，the width，指FIFO一次读写操作的数据位；

FIFO深度，THE DEEPTH，指FIFO可以存储多少个N位的数据；

满标志，FIFO已满或将要满时送出的一个信号，以阻止FIFO的血操作继续向FIFO中写数据而造成溢出（overflow）；

空标志，阻止FIFIO的读操作；

1.quartus中直接调用FIFO IP核

2.verilog

异步FIFO代码：

module fifo_module
(
    input CLK,
     input RSTn,

     input Write_Req,
     input [:]FIFO_Write_Data,

     input Read_Req,
     output [:]FIFO_Read_Data,

     output Full_Sig,
     output Empty_Sig,

     /**********************/

     output [:]SQ_rS1,
     output [:]SQ_rS2,
     output [:]SQ_rS3,
     output [:]SQ_rS4,
     output [:]SQ_Count

     /**********************/
);

    /************************************/

     parameter DEEP = 'd4;

     /************************************/

    reg [:]rShift [DEEP:];
     reg [:]Count;
     reg [:]Data;

     always @ ( posedge CLK or negedge RSTn )
          if( !RSTn )
              begin

                    rShift[] <= 'd0; rShift[1] <= 8'd0; rShift[] <= 'd0;
                     rShift[] <= 'd0; rShift[4] <= 8'd0;
                     Count <= 'd0;
                     Data <= 'd0;

                end
          else if( Read_Req && Write_Req && Count < DEEP && Count >  )
              begin
                    rShift[] <= FIFO_Write_Data;
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];
                     Data <= rShift[ Count ];    //若深度较大，则需多行代码，且存储器间存在频繁的数据转移
                end
         else if( Write_Req && Count < DEEP )
              begin

                    rShift[] <= FIFO_Write_Data;
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];

                     Count <= Count + 'b1;
                end
        else if( Read_Req && Count >  )
              begin
                     Data <= rShift[Count];
                     Count <= Count - 'b1;
                end

    /************************************/

     assign FIFO_Read_Data = Data;
     assign Full_Sig = ( Count == DEEP ) ? 'b1 : 1'b0;
     assign Empty_Sig = ( Count ==  ) ? 'b1 : 1'b0;

     /************************************/

     assign SQ_rS1 = rShift[];
     assign SQ_rS2 = rShift[];
     assign SQ_rS3 = rShift[];
     assign SQ_rS4 = rShift[];
     assign SQ_Count = Count;

     /************************************/

endmodule

第一，FIFO 的调用绝对需要控制信号
第二，Full_Sig  和  Empty_Sig  是不适合同步 FIFO 的写操作

改进同步FIFO，放弃了  Empty_Sig  和  Full_Sig，取而代之的是  Left_Sig  。作用如
名字般，该信号用来反馈出  FIFO  目前的“空格数目”

module fifo_module_2
(
    input CLK,
     input RSTn,

     input Write_Req,
     input [:]FIFO_Write_Data,

     input Read_Req,
     output [:]FIFO_Read_Data,

     output [:]Left_Sig
);

       /************************************/

     parameter DEEP = 'd4;

     /************************************/

    reg [:]rShift [DEEP:];
     reg [:]Count;
     reg [:]Data;

     always @ ( posedge CLK or negedge RSTn )
          if( !RSTn )
              begin

                    rShift[] <= 'd0; rShift[1] <= 8'd0; rShift[] <= 'd0;
                     rShift[] <= 'd0; rShift[4] <= 8'd0;
                     Count <= 'd0;
                     Data <= 'd0;

                end
          else if( Read_Req && Write_Req && Count < DEEP && Count >  )
              begin
                    rShift[] <= FIFO_Write_Data;
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];
                     Data <= rShift[ Count ];
                end
         else if( Write_Req && Count < DEEP )
              begin

                    rShift[] <= FIFO_Write_Data;
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];
                     rShift[] <= rShift[];

                     Count <= Count + 'b1;
                end
        else if( Read_Req && Count >  )
              begin
                     Data <= rShift[Count];
                     Count <= Count - 'b1;
                end

    /************************************/

     assign FIFO_Read_Data = Data;
     assign Left_Sig = DEEP - Count;

     /************************************/

endmodule

仿真激励文本

`timescale  ps/  ps
module fifo_module_2_simulation();

    reg CLK;
     reg RSTn;

    reg Write_Req;
    reg [:]FIFO_Write_Data;

    reg Read_Req;

    wire [:]FIFO_Read_Data;

    wire [:]Left_Sig;

     /*******************/

    fifo_module_2 U1
     (
         .CLK(CLK),
          .RSTn( RSTn ),
          .Write_Req(Write_Req),
          .FIFO_Write_Data(FIFO_Write_Data),
         .Read_Req(Read_Req),
         .FIFO_Read_Data(FIFO_Read_Data),
          .Left_Sig(Left_Sig)
    );

     /*******************/

    initial
    begin
        RSTn = ; #; RSTn = ;
        CLK = ; forever # CLK = ~CLK;
    end    

    /*******************/

     reg [:]i;

    always @ ( posedge CLK or negedge RSTn )
         if( !RSTn )
              begin

                  i <= 'd0;
                  Write_Req <= 'b0;
                  Read_Req <= 'b0;
                  FIFO_Write_Data <= 'd0;

                end
          else
              case( i )

                     /**********/

                    :
                     begin Write_Req <= 'b1; Read_Req <= 1'b0; FIFO_Write_Data <= 'd1; i <= i + 1'b1; end

                     :
                     begin Write_Req <= 'b1; Read_Req <= 1'b0; FIFO_Write_Data <= 'd2; i <= i + 1'b1; end

                     :
                     begin Write_Req <= 'b1; Read_Req <= 1'b0; FIFO_Write_Data <= 'd3; i <= i + 1'b1; end

                     :
                     begin Write_Req <= 'b1; Read_Req <= 1'b0; FIFO_Write_Data <= 'd4; i <= i + 1'b1; end

                     /**********/

                     :
                     begin Write_Req <= 'b0; Read_Req <= 1'b1; i <= i + 'b1; end

                     :
                     begin Write_Req <= 'b0; Read_Req <= 1'b1; i <= i + 'b1; end

                     :
                     begin Write_Req <= 'b0; Read_Req <= 1'b1; i <= i + 'b1; end

                     :
                     begin Write_Req <= 'b0; Read_Req <= 1'b1; i <= i + 'b1; end

                     /**********/

                     : // 0 + 1 < 1
                     if( Left_Sig <=  ) begin Write_Req <= 'b0; i <= i + 1'b1; end
                     else begin Write_Req <= 'b1; Read_Req <= 1'b0; FIFO_Write_Data <= FIFO_Write_Data + 'b1; end

                    : // >  DEEP - 1
                     if( Left_Sig >=  )begin Read_Req <= 'b0; i <= i + 1'b1; end
                     else begin Write_Req <= 'b0; Read_Req <= 1'b1; end 

                     /**********/

                     :
                     if( Left_Sig >=  ) begin Write_Req <= 'b1; FIFO_Write_Data <= 8'd5; i <= i + 'b1; end
                     else begin Write_Req <= 'b0; i <= i + 1'b1; end

                     :
                     if( Left_Sig >=  ) begin Write_Req <= 'b1; FIFO_Write_Data <= 8'd6; i <= i + 'b1; end
                     else begin Write_Req <= 'b0; i <= i + 1'b1; end

                     :
                     begin 

                         if( Left_Sig >=  ) begin Write_Req <= 'b1; FIFO_Write_Data <= 8'd7; end
                          else Write_Req <= 'b0;

                          if( Left_Sig <=  ) begin Read_Req <= 'b1; end
                          else Read_Req <= 'b0;

                          i <= i + 'b1; 

                     end

                     :
                     begin 

                         if( Left_Sig >=   ) begin Write_Req <= 'b1; FIFO_Write_Data <= 8'd8; end
                          else Write_Req <= 'b0;

                          if( Left_Sig <=  ) begin Read_Req <= 'b1; end
                          else Read_Req <= 'b0;

                          i <= i + 'b1; 

                     end

                     :
                     if( Left_Sig <=  ) begin Write_Req <= 'b0; Read_Req <= 1'b1; i <= i + 'b1; end
                     else begin Read_Req <= 'b0; i <= i + 1'b1; end

                     :
                     if( Left_Sig <=  ) begin Read_Req <= 'b1; i <= i + 1'b1; end
                     else begin Read_Req <= 'b0; i <= i + 1'b1; end

                     :
                     begin Read_Req <= 'b0; i <= 5'd16; end

                endcase

endmodule