FPGA控制HC595

/*****************************************************************************
Copyright: 2013
File name: led.v
Description: 使用HC595驱动数码管
Author:
Version: v1.0
Date: 2013.05.09
History: 无
Connect:P3.4->pin114
    P3.5->pin116
    P3.6->pin118 
*****************************************************************************/
module HC595(CLOCK,RESET,RLK,CLK,DAT,BEEP);
input CLOCK,RESET;
output reg  RLK,CLK,DAT;
output BEEP;
parameter T1s=31'd2_000_0000;
reg [8:0] t;
reg  [8:0] S;
reg [31:0] cnt;
reg [3:0] num;
assign BEEP=1'b1;
always @ (posedge CLOCK or negedge RESET)
if(!RESET)
 begin
  RLK<=0;
  DAT<=0;
  CLK<=0;
  t<=0;
 // S<=led(0);
  cnt<=0;
  num<=0;
 end
       else
        begin
         cnt<=cnt+1;
         if(cnt==T1s)
          begin
           cnt<=0;
           num<=num+1;
           if(num>8)
           num<=0;
          end
         case(t)
         0,2,4,6,8,10,12,14:
         begin CLK<=0;DAT<=S>>7;t<=t+1;end
         1,3,5,7,9,11,13,15:
         begin CLK<=1;S<=S<<1;t<=t+1;end
         16:begin t<=t+1;RLK<=0;end
         17:begin t<=t+1;RLK<=1;end
         18:begin t<=0;RLK<=0;CLK<=0;S<=led(num);end
         endcase
        end
function [7:0] led;
input [3:0] key;
case(key)
0:led=8'hc0;
1:led=8'hf9;
2:led=8'ha4;
3:led=8'hb0;
4:led=8'h99;
5:led=8'h92;
6:led=8'h82;
7:led=8'hf8;
8:led=8'h80;
9:led=8'h90;
default:led=8'hzz;
endcase
endfunction
endmodule