what is delta simulation time

In digital logic simulation, a delta cycles are evaluation of expressions, followed by value updates, causing more evaluations, and more value updates, and so on. Each time through the loop is one delta cycle. Different languages have specific definitions of what can happen in a delta cycle, and in most cases, simulation time does not advance in a delta cycle until there is nothing left to do at the current simulation time. Then simulation time is stepped to the next scheduled activity. So there can be one or many delta cycles in a time step. This is the case for SystemVerilog and VHDL.

For synchronous processes, delta delays may be ignored.

If your testbench uses wait statements, you will
discover delta delays. Sim signals will not change
value until a wait is encountered.

Consider writing your testbench in a synchronous
style, using waits only for the sim clock generator.

This not only eliminates the non-stylish "wait for 0 ns",
but it keeps your brain in synchronous mode at all times.

Delta delay affects every assignment to a signal.

A concurrent signal assignment is a process. Take,
for example:

architecture foo of bar is
signal a,b,c: bit;
begin
a <= b and c;
end;

The concurrent assignment "a <= b and c;" is EXACTLY
equivalent to the process

process(b,c) begin
a <= b and c;
end process;

which, in its turn, is exactly equivalent to

process begin
a <= b and c;
wait on b,c;
end process;

In all three cases, the signal assignment suffers a delta delay.

Delta delays allow a discrete-event simulator to be deterministic
without the need for (explicit) mutual exclusion mechanisms.

As Verilog shows, it is possible to define a simulator in which
some signal assignments do NOT suffer delta delays, and yet
retain deterministic behaviour if the user is careful enough. 
The delta delay mechanism is available in Verilog, through 
nonblocking assignment, and is effectively essential when 
writing clock-synchronous descriptions. I say "effectively 
essential" because there are other ways to write clock-
synchronous models, without using nonblocking 
assignment; but they are extremely clumsy and 
error-prone.