full_case & parallel_case

case中的full_case与parallel_case讨论：

1)术语介绍： 整个case模块叫做：case_statement，注释部分叫做case_statement_header

case (case_expression)  //synopsys full_case/parallel_case

case_item1 ：case_item_statement1;

case_item2 ：case_item_statement2;

case_item3 ：case_item_statement3;

case_item4 ：case_item_statement4;

endcase

casez，使用“？”来表示任意值。

casex，使用“？，z”来表示任意值，不建议使用。

2)如果使用full_case显式表示not_full_case，其他的没有的case_item值，not care。

full_case下也可能会出现latch,not_full_case下也可能不会出现latch(可以通过赋初值来避免)

module addrdecode (m0,m1,ce,addr);                                                                         module addrdecode (m0,m1,ce,addr);

output  m0,m1,ce;                                                                                                     output  m0,m1,ce;

input [31:0]addr;                   //产生3个latch                                                                input [31:0]addr;                   //无latch

reg m0,m1,ce;                                                                                                           reg m0,m1,ce;

always @(addr)                                                                                                          always @(addr)

casez(addr) // synopsys full_case                                                                                {m0,m1,ce} = 3'b111;

2'b10: {m0,m1} = 2'b10;                                                                                        casez(addr) // synopsys full_case

2'b11: {m0,m1} = 2'b01;                                                                                             2'b10: {m0,m1} = 2'b10;

2'b0?: {ce} = 1'b0;                                                                                                      2'b11: {m0,m1} = 2'b01;

endcasez                                                                                                                         2'b0?: {ce} = 1'b0;

endmodule                                                                                                                              endcasez

endmodule

3)如果使用parallel_case显式表示not_parallel_case，可能有一些值会over_lap。

parallel_case用在not_parallel的case中，其中overlap的部分如果有效，会导致gate_level电路工作异常。

建议尽量不显式使用full_case和parallel_case来进行建模，对于平行结构多使用case，有优先级的结构多使用if-else。