[转]OrCAD PSpice DIODE model parameter

1.从OrCAD PSpice help文档：

2.国外网站的相关介绍：

The DC characteristics of the diode are determined by the parameters IS, N, and the ohmic resistance RS. Charge storage effects are modeled by a transit time, TT, and a nonlinear depletion layer capacitance which is determined by the parameters CJO, VJ, and M. The temperature dependence of the saturation current is defined by the parameters EG, the band gap energy and XTI, the saturation current temperature exponent. The nominal temperature at which these parameters were measured is TNOM, which defaults to the circuit-wide value specified on the .OPTIONS control line. Reverse breakdown is modeled by an exponential increase in the reverse diode current and is determined by the parameters BV and IBV (both of which are positive numbers).

3. 国外网站关于PSpice 其它模型的参数介绍：如（三极管，达林顿管，场效应管，二极管）

Spice models

• Introduction
• The MOD model file
• The ZMODELS.LIB library file
• Model parameters and limitations
  • Bipolars
  • Darlingtons
  • MOSFETs
  • Diodes
• Further information

Introduction

Zetex have created Spice models for a range of semiconductor components. Models included are Schottky and varicap, high-performance bipolar (high current, low VCE(sat)), higher voltage bipolar, bipolar Darlington and MOSFET transistors. This range is continuously under review as new products are introduced and retrospective models are generated for existing products.

The Spice models are available in two formats:

1. A separate Spice model text file for each Zetex device type for which a model is presently available. These can be accessed from the Product Quickfinder
2. All the available Zetex device models are collected together into a single .LIB text file called ZMODELS.LIB.

A generic symbol library file is available called ZETEXM.SLB that enables Windows® versions of PSpice to use the Zetex spice models. Further information on the symbol library, including installation instructions will be found in the text file called ZETEXM.TXT

The MOD Model File

Each of these files is a Spice model for a single device. They can be loaded into your simulation simply by employing the Spice command <.include device_name.mod>. Only the device types specifically required by the circuit under simulation need be included in this way. All diode and bipolar transistor models are simple <.model> files. However, Darlington transistors and MOSFET models are multi-component subcircuits and as such are supplied as <.subckt> files.

The diode models should be included in circuit files using the normal Spice reference <Dnum Anode_node Cathode_node Device_name>.

Bipolar transistor models should be included using <Qnum Collector_node Base_node Emitter_node Device_name>.

All other models should be referenced as subcircuits i.e. in the form <Xnum Collector_node Base_node Emitter_node Device_name> for Darlington transistors, and <Xnum Drain_node Gate_node Source_node Device_name> for MOSFETs.

The ZMODELS.LIB Library File

Users may prefer to use the model library. This library is a collection of all Zetex Spice models exactly as they appear in the individual model files. By using the statement <.lib zmodels.lib>, Spice will be able to access any model within the library without the need for multiple <.include> statements.

Note:
All subcircuits, whether in the library or as individual model files use the same connection sequence as Spice for single element models, thus easing their use.

Model parameters and limitations

• Bipolars
• Darlingtons
• MOSFETs
• Diodes

Bipolars

All bipolar transistor and Darlington models are based on Spice's modified Gummel-Poon model. A typical model for a single transistor is shown as follows:

*Zetex FMMT493A Spice Model v1.0 Last Revised 30/3/06
*
.MODEL FMMT493A NPN IS =6E-14 NF =0.99 BF =1100 IKF=1.1
+NK=0.7 VAF=270 ISE=0.3E-14 NE =1.26 NR =0.98 BR =70 IKR=0.5
+VAR=27 ISC=1.2e-13 NC =1.2 RB =0.2 RE =0.08 RC =0.08 RCO=8
+GAMMA=5E-9 CJC=15.9E-12 MJC=0.4 VJC=0.51 CJE=108E-12
+MJE=0.35 VJE=0.7 TF =0.8E-9 TR =55e-9 XTB=1.4 QUASIMOD=1
*

In the bipolar model:

• IS and NF control Icbo and the value of Ic at medium bias levels.
• ISE and NE control the fall in hFE that occurs at low Ic.
• BF controls peak forward hFE and XTB controls how it varies with temperature.
• BR controls peak reverse hFE i.e. collector and emitter reversed.
• IKF and NK control the current and the rate at which hFE falls at high collector currents.
• IKR controls where reverse hFE falls at high emitter currents.
• ISC and NC controls the fall of reverse hFE at low currents.
• RC, RB and RE add series resistance to these device terminals.
• VAF controls the variation of collector current with voltage when the transistor is operated in its linear region.
• VAR is the reverse version of VAF.
• CJC, VJC and MJC control Ccb and how it varies with Vcb.
• CJE, VJE and MJE control Cbe Ccb and how it varies with Veb.
• TF controls Ft and switching speeds.
• TR controls switching storage times.
• RCO, GAMMA, QUASIMOD control the quasi-saturation region.

Some standard bipolar transistor Spice models may not include a parameter that allows BF, the hFE parameter, to vary with temperature. If XTB is absent it defaults to zero, e.g. no temperature dependence. If hFE temperature effects are of interest and XTB is not modeled then the following values may be used to provide an estimate or a starting point for further investigation:

Polarity XTB NPN 1.6 PNP 1.9

It is suggested that the appropriate datasheet hFE profile is examined, and a Spice test circuit created that simulates the device in question and generates a set of hFE curves. Two or three such iterations should normally be sufficient to define a value for XTB in each case. Please remember that these notes are only a rough guide as to the effect of model parameters. Also, many of the parameters are interdependent so adjusting one parameter can affect many device characteristics.

At Zetex, we have endeavored to make the models perform as closely to actual samples as possible but some compromises are forced which can result in simulation errors under some circumstances. The main areas of error observed so far have been:

• Spice is often over optimistic in the hFE a transistor will give when operated above its data sheet current ratings. This is particularly true for a high voltage transistor operated at a low collector-emitter voltage and quasi-saturation parameters RCO, GAMMA and QUASIMOD have been introduced to improve the models in this region.
• Spice can be pessimistic when predicting switching storage time when current is extracted from the base of a transistor to speed turn-off.

Darlingtons

These are subcircuits using a standard transistor model. A Darlington model is shown as follows:

*
*Zetex FZT605 Spice Model v1.0 Last revision 27/04/05
*
.SUBCKT FZT605 1 2 3
* C B E
Q1 1 2 4 SUB605
Q2 1 4 3 SUB605 3.46
*
.MODEL SUB605 NPN IS=4.8E-14 BF=170 etc.
.ENDS FZT605
*
*$

Note:
Because Zetex Darlingtons are monolithic, the two transistors used are identical in all respects other than size. (The number at the end of the Q2 line multiplies the size of the SUB605 transistor by 3.46 - the ratio of the areas of the input and output transistors for this device).

MOSFETs

None of Spice's standard MOSFET models fit the characteristics of trench or vertical MOSFETs too well. Consequently the models of MOSFET's supplied have been made using subcircuits that include additional components to improve simulation accuracy. A typical less complex MOSFET model is shown as follows:

*
*ZETEX ZXMN3A14F Spice Model v1.0 Last revision 31/5/06
*
.SUBCKT ZXMN3A14F 30 40 50
*------connections-------D-G-S
M1 6 2 5 5 Nmod L=1.16E-6 W=0.76
M2 5 2 5 6 Pmod L=1.3E-6 W=0.35
RG 4 2 4.5
RIN 2 5 1E12
RD 3 6 Rmod 0.04
RS 5 55 Rmod 0.015
RL 3 5 3E9
C1 2 5 8.5E-12
C2 3 4 3E-12
D1 5 3 Dbodymod
LD 3 30 0.5E-9
LG 4 40 1.0E-9
LS 55 50 1.0E-9
.MODEL Nmod NMOS (LEVEL=3 TOX=5.5E-8 NSUB=5E16 VTO=2.13
+KP=2.5E-5 NFS=2E11 KAPPA=0.06 UO=650 IS=1E-15 N=10)
.MODEL Pmod PMOS (LEVEL=3 TOX=5.5E-8 NSUB=1.5E16
+TPG=-1 IS=1E-15 N=10)
.MODEL Dbodymod D (IS=6E-13 RS=.025 IKF=0.1 TRS1=1.5e-3
+CJO=150e-12 BV=33 TT=12e-9)
.MODEL Rmod RES (TC1=2.8e-3 TC2=0.8E-5)
.ENDS ZXMN3A14F
*
*$
*

In the MOSFET model:

• L relates to a process parameter.
• W relates to a process parameter.
• TOX relates to a process parameter.
• NSUB relates to a process parameter.
• VTO defines Vgs(th).
• KP controls Gm.
• NFS fast surface state density.
• KAPPA saturation field factor.
• UO mobility.
• RS and RD add series terminal resistance with temperature characteristic modeled.
• IS and N suppress the behavior of the MOSFET model's default body diode.
• CGDO, derived from process related parameters, controls Crss.
• CGSO, derived from process related parameters, controls Ciss.
• CBD, derived from process related parameters, controls Coss.

In this trench MOSFET the NMOS models the walls of the trench and the PMOS models the bottom of the trench. Added to the Spice standard MOSFET models are a gate resistor to control switching speeds, gate source and drain-source resistors to control leakage, drain and source series resistance, a drain-source diode to accurately reflect the performance of the MOSFET's body diode and inductors to model inductance inside the package.

Recent MOSFET models mirror the performance of the real devices reasonably well in most areas. One area not covered well by the older less complex models is the way that Crss and Coss vary with drain-source voltage. Thus if the less complex models are used at a drain-source voltage well away from datasheet capacitance definition voltages and capacitance is critical, then the values used for CGSO and CGDO may need adjustment.

Diodes

The Tuner diode and Schottky Diode ranges use a standard Spice diode model and a typical file appears as follows:

*
*Zetex ZC830A Spice Model v1.0 Last Revised 4/3/92
*
.MODEL ZC830A D IS=5.355E-15 N=1.08 RS=0.1161 XTI=3
+ EG=1.11 CJO=19.15E-12 M=0.9001 VJ=2.164 FC=0.5
+ BV=45.1 IBV=51.74E-3 TT=129.8E-9
+ ISR=1.043E-12 NR=2.01
*
*NOTES: FOR RF OPERATION ADD PACKAGE INDUCTANCE 0F 2.5E-9H AND SET
*RS=0.68 FOR 2V, 0.60 FOR 5V, 0.52 FOR 10V OR 0.46 FOR 20V BIAS.
*
*$
*

In the diode model:

• IS controls forward and reverse current against voltage.
• N controls forward current against voltage.
• RS controls forward voltage at high current.
• CJO, M and VJ control variation of capacitance with voltage.
• BV and IBV control reverse breakdown characteristics.
• TT controls switching reverse recovery characteristics.
• ISR and NR control reverse biased leakage.
• EG controls barrier height.
• FC forward bias depletion capacitance coefficient.

For operation at RF (which would be the norm for a varicap or tuner diode) it is recommended that a 2.5nH series inductor be added as an extra circuit element to correct for the inherent package inductance, this value will change with package size.

Also for some models data is available to enable the RS parameter better model Q at voltages other than the specified condition.

(原文地址：http://hi.baidu.com/rdtech/item/fe0138ea7aa36af2e0a5d483)