【黑金教程笔记之005】【建模篇】【Lab 04 消抖模块之二】—笔记

实验四和实验三的区别在于输出。实验三是检测到由高到低的电平变化时就拉高输出，检测到由低到高的电平变化时就拉低输出。而实验四检测到由高到低的电平变化时产生一个100ms的高脉冲。当检测到由低到高的电平变化时，只有消抖操作。

模块：

 /***********************************************************
 module name: detect_module.v
 function: detect pin's level change

 by yf.x
 2014-11-05

 ************************************************************/

 module detect_module(
 CLK,
 RST_n,
 Pin_in,
 H2L_Sig,
 L2H_Sig
 );

 input CLK;
 input RST_n;
 input Pin_in;
 output H2L_Sig;
 output L2H_Sig;

 /**************************************************************/
 //DE2-115 use 50MHz oscillator,50M*0.0001-1=4_999
 parameter T100us='d4999;

 /**************************************************************/

 reg [:]count1;
 reg isEn;

 always @(posedge CLK or negedge RST_n)    //100us timer
 if(!RST_n)
   begin
     count1<='d0;
      isEn<='b0;
   end
 else if(count1==T100us)
   isEn<='b1;
 else
   count1<=count1+'b1;

  /***********************************************************/

 reg H2L_F1;
 reg H2L_F2;
 reg L2H_F1;
 reg L2H_F2;

 always @(posedge CLK or negedge RST_n)
 if(!RST_n)
   begin
     H2L_F1<='b1;
      H2L_F2<='b1;
     L2H_F1<='b0;
     L2H_F2<='b0;
   end
 else
   begin
     H2L_F1<=Pin_in;
     H2L_F2<=H2L_F1;
     L2H_F1<=Pin_in;
     L2H_F2<=L2H_F1;
   end

 /*****************************************************/

 assign H2L_Sig=isEn?(!H2L_F1&H2L_F2):'b0;
 assign L2H_Sig=isEn?(!L2H_F2&L2H_F1):'b0;

 /*****************************************************/

 endmodule

 /***************************************************
 module name: delay_module.v
 function: delay 10ms.

 by yf.x
 2014-11-05

 ***************************************************/

 module delay_module(
 CLK,
 RST_n,
 H2L_Sig,
 L2H_Sig,
 Pin_out
 );

 input CLK;
 input RST_n;
 input H2L_Sig;
 input L2H_Sig;
 output Pin_out;

 /**************************************************/
 //5M*0.001-1=49_999
 parameter T1ms='d49_999;

 /**************************************************/

 reg [:]count1;

 always @(posedge CLK or negedge RST_n)
 if(!RST_n)
   count1<='d0;
 else if(iscount && count1==T1ms)
   count1<='d0;
 else if(iscount)
   count1<=count1+'b1;
 else if(!iscount)
   count1<='d0;

 /****************************************************/

 reg [:]count_ms;

 always @(posedge CLK or negedge RST_n)
 if(!RST_n)
   count_ms<='d0;
 else if(iscount && count1==T1ms)
   count_ms<=count_ms+'b1;
 else if(!iscount)
   count_ms<='d0;

 /*******************************************************/

 reg iscount;
 reg rPin_out;
 reg [:]i;

 always @(posedge CLK or negedge RST_n)
 if(!RST_n)
   begin
     iscount<='b0;
     rPin_out<='b0;
     i<='d0;
   end
 else
   case(i)
     'd0:
     if(H2L_Sig)
       i<='d1;
     else if(L2H_Sig)
        i<='d3;

      'd1:
      if(count_ms=='d10)
      begin
        iscount<='b0;
        rPin_out<='b1;
        i<='d2;
      end
      else
        iscount<='b1;

      'd2:
      if(count_ms=='d100)
      begin
        iscount<='b0;
        rPin_out<='b0;
        i<='d0;
      end
      else
        iscount<='b1;

     'd3:
      if(count_ms=='d10)
      begin
        iscount<='b0;
        i<='d0;
      end
      else
        iscount<='b1;
     endcase

 /**************************************************/

 assign Pin_out=rPin_out;

 /**************************************************/

 endmodule

 /****************************************
 module name: debounce_module.v
 function: debounce a key
 pin assignments(for DE2-115):
 ---------------------------------
 CLK----------------------CLOCK_50
 RST_n--------------------KEY[0]
 Pin_in-------------------KEY[3]
 Pin_out------------------LEDG[3]

 by yf.x
 2014-11-05

 ****************************************/

 module debounce_module(
 CLK,
 RST_n,
 Pin_in,
 Pin_out
 );

 input CLK;
 input RST_n;
 input Pin_in;
 output Pin_out;

 /*******************************/

 wire H2L_Sig;
 wire L2H_Sig;

 detect_module u0(
 .CLK(CLK),
 .RST_n(RST_n),
 .Pin_in(Pin_in),    //input from top
 .H2L_Sig(H2L_Sig),  //output to u1
 .L2H_Sig(L2H_Sig)   //output to u1
 );

 /***************************************/

 delay_module u1(
 .CLK(CLK),
 .RST_n(RST_n),
 .H2L_Sig(H2L_Sig),  //input from u1
 .L2H_Sig(L2H_Sig),   //input from u1
 .Pin_out(Pin_out)   //output to top
 );

 /***************************************/

 endmodule

实验四说明：

实验四和实验三代码部分的区别在delay_module.v的case部分。