简易数据加密传输电路（VHDL）（原创）

 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.std_logic_unsigned.ALL;

 ENTITY KEKE IS  --定义实体wsj1
     GENERIC(n : positive := );

     PORT(CLK:IN STD_LOGIC;--时钟信号
         CTL:IN STD_LOGIC;--控制信号
         V1:BUFFER STD_LOGIC;--假设伪随机序列1作为待价密数据
          V2:BUFFER STD_LOGIC;--伪随机序列二作为密钥数据流v2
           V3:BUFFER STD_LOGIC;--V3为异或后生成的加密数据串行输出
           V4:BUFFER STD_LOGIC;--解密数据流应该和密钥数据流v2相同
           V5:BUFFER STD_LOGIC--v3和v4异或解密得到结果v5
         );
 END KEKE;

 ARCHITECTURE BEHAV OF KEKE IS

 SIGNAL C0,C1,C2,C3,C4,C5,C6,C7:STD_LOGIC;--伪随机序列1作为待价密数据
 SIGNAL A0,A1,A2,A3,A4,A5,A6,A7:STD_LOGIC;--伪随机序列二作为密钥数据流v2 和解密数据流v4

 BEGIN
   ----伪随机序列1作为待价密数据
     PROCESS(CLK, CTL)
         BEGIN
             IF CLK'EVENT AND CLK='' THEN
                 IF ( CTL='') THEN
                     C7<='';C6<='';C5<='';C4<='';C3<='';C2<='';C1<='';C0<='';V1<=C7;
                 ELSE
                     C1<=C0;C2<=C1; C3<=C2;C4<=C3;C5<=C4;C6<=C5;C7<=C6;
                     C0<=C7 XOR C4 XOR C3 XOR C2  ;
                     V1<=C7;
                 END IF;
             END IF;
     END PROCESS;
     ----伪随机序列二作为密钥数据流v2 和解密数据流v4
     PROCESS(CLK, CTL)     --设置敏感量
         BEGIN
             IF CLK'EVENT AND CLK='' THEN
                 IF ( CTL='') THEN
                     A7<='';A6<='';A5<='';A4<='';A3<='';A2<='';A1<='';A0<='';V2<=A7;V4<=A7;
                 ELSE
                     A1<=A0;A2<=A1; A3<=A2;A4<=A3;A5<=A4;A6<=A5;A7<=A6;
                     A0<=A7 XOR A1;
                     V2<=A7;
                    V4<=A7;
                 END IF;
             END IF;
     END PROCESS;
     ----v3密文数据为v1v2异或得到
    V3<=V1 xor V2;
     ----v5密文数据为v3v4异或得到明文数据应该和v1一样
     V5<=V3 xor V4;
 END BEHAV;