Assembler Code Content of ROM MOV R10,R11 MOV R10,R11 Length: One or two words Operation: Move the content of R10 to R11. R10 is not affected. Comment: Valid for source and destination Example: MOV  R10, R11…

The status register (SR/R2), used as a source or destination register, can be used in the register mode only addressed with word instructions. The remaining combinations of addressing modes are used to support the constant generator.…

JC Jump if carry setJHS  Jump if higher or same Syntax JC label JHS label Operation If C = 1: PC + 2 × offset −> PC If C = 0: execute following instruction Description The status register carry bit (C) is tested. If it is set, the 10-bit signed offse…

JMP  Jump unconditionally Syntax   JMP  label Operation PC + 2 × offset −> PC Description The 10-bit signed offset contained in the instruction LSBs is added to the program counter. Status Bits Status bits are not affected. Hint: This one-word instru…

Assembler Code Content of ROMMOV @R10+,0(R11)   MOV @R10+,0(R11) Length: One or two words Operation: Move the contents of the source address (contents of R10) to the destination address (contents of R11). Register R10 is incremented by 1 for a byte o…

Byte and word issues The MSP430 is byte-addressed, and little-endian. Word operands must be located at even addresses 1 Appending “.b” to an instruction makes it a byte operation. A byte instruction with a register destination clears the high 8 bits…

MOV[.W]   Move source to destinationMOV.B Move source to destination Syntax MOV  src,dst  or       MOV.W  src,dst MOV.B src,dst Operation src −> dst Description The source operand is moved to the destination.The source operand is not affected. The pr…

CMP[.W]  Compare source and destinationCMP.B  Compare source and destination Syntax  CMP src,dst or CMP.W src,dst CMP.B  src,dst Operation dst + .NOT.src + 1 or (dst − src) Description The source operand is subtracted from the destination operand. Th…

Processor operations mostly involve processing data. This data can be stored in memory and accessed from thereon. However, reading data from and storing data into memory slows down the processor, as it involves complicated processes of sending the da…

A data processor (104) is described. The data processor (104) is capable of decoding and executing a first instruction (212) of a first instruction set and a second instruction (213-219) in a second instruction set wherein the first instruction (212)…