Minimizing the overall power conservation in a symmetric multiprocessor system disposed in a system-on-chip (SoC) depends on using voltage islands operated at different voltages such that similar circuits will perform at significantly different level…

Various embodiments of methods and systems for thermally aware scheduling of workloads in a portable computing device that contains a heterogeneous, multi-processor system on a chip ("SoC") are disclosed. Because individual processing components…

BACKGROUND OF THE INVENTION This relates to Input/Output (I/O) performance in a host system having multiple processors, and more particularly, to efficient usage of multiple processors in handling I/O completions by using interrupt affinity schemes t…

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals…

Within a multi-processing system including a plurality of processor cores 4, 6operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region.…

A pending tag system and method to maintain data coherence in a processing node during pending transactions in a transaction pipeline. A pending tag storage unit may be coupled to a cache controller and configured to store pending tags each indicativ…

An improved memory model and implementation is disclosed. The memory model includes a Total Store Ordering (TSO) and Partial Store Ordering (PSO) memory model to provide a partial order for the memory operations which are issued by multiple processor…

https://en.wikipedia.org/wiki/Unified_shader_model In the field of 3D computer graphics, the Unified Shader Model (known in Direct3D 10 as "Shader Model 4.0") refers to a form ofshader hardware in a graphical processing unit (GPU) where all of t…

An architecture for an extended multiprocessor (XMP) computer system is provided. The XMP computer system includes multiple SMP nodes. Each SMP node includes an XMP interface and a repeater structure coupled to the XMP interface. The SMP nodes are co…

A multiprocessing system having a plurality of processing nodes interconnected by an interconnect network. To optimize performance during spin-lock operations, a home agent prioritizes the servicing of read-to-own (RTO) transaction requests over the…