Key Features High-performance FPGA configuration and PROM/CPLD programming Includes innovative FPGA-based acceleration firmware encapsulated in a small form factor pod attached to the cable Supports JTAG and Slave-Serial programming topologies Firmwa
http://www.freelabs.com/~whitis/electronics/jtag/ One of the big issues in making a JTAG pod is level translation. The state of level translation ICs leaves a LOT to be desired. You would think that there would be a lot of chips that you could apply
http://www.planetanalog.com/author.asp?section_id=3041&doc_id=563055 Jonathan Harris, Product Applications Engineer, Analog Devices, 6/2/2014 As I thought about where to go with the next blog, I looked over the comments and questions from my previous
Linear Technology's recently introduced LTC4300 chip buffers I2C clock and data lines to and from a hot-swappable card. This task is difficult because the IC must work bidirectionally, meaning that you can simultaneously and actively drive both sides