verilog中的有符号数理解（转）

verilog中的有符号数运算

有符号数的计算：若有需要关于有号数的计算，应当利用Verilog 2001所提供的signed及$signed()机制。

Ex:

input  signed [7:0] a, b;

output  signed [15:0] o;

assign o = a * b;

or

input   [7:0] a, b;

output   [15:0] o;

wire signed [15:0] o_sgn;

assisn o_sgn = $signed(a) * $signed(b);

assign o = $unsigned(o_sgn);

正负号的扩展：应多加利用Verilog的implicity signed extension，避免手动进行转换。

Ex:

input signed [7:0] a, b;

input signed [8:0] o;

assign o = a + b; // Verilog会自动进行符号的扩展。有号数与无号数的混合计算：不要在同一个verilog叙述中进行有号数与无号数的计算。应该要分成个别独立的叙述。在一个verilog叙述中只要有一个无号数的操作数，整个算式将被当成无号数进行计算。（常数默认为无符号数）

input   [7:0] a;

input  signed [7:0] b;

output signed [15:0] o; // Don't do this: assign o = a * b;

// The $signed({1'b0, a}) can convert the unsigned number to signednumber.a

ssign o = $signed({1'b0, a}) * b;

input signed [7:0] a;output signed [15:0] o;

// Don't do this: assign o = a * 8'b10111111;

// Use $signed() system taskassign o = a * $signed(8'b10111111);

// or sb keyword.assign o = a * 8'sb10111111;part-select运算过后的操作数是无号数。就算是选择的范围包含整个register或wire。input signed [7:0] a;

input signed [7:0] b;

output signed [15:0] o1, o2; // Don't do this:

assign o1 = a[7:0];assign o1 = a;// Don't do this: assign o2 = a[6:0] * b;

assign o2 = $signed(a[6:0]) + b