Verilog MIPS32 CPU（五）-- CP0

• Verilog MIPS32 CPU（一）-- PC寄存器
• Verilog MIPS32 CPU（二）-- Regfiles
• Verilog MIPS32 CPU（三）-- ALU
• Verilog MIPS32 CPU（四）-- RAM
• Verilog MIPS32 CPU（五）-- CP0
• Verilog MIPS32 CPU（六）-- MDU
• Verilog MIPS32 CPU（七）-- DIV、DIVU
• Verilog MIPS32 CPU（八）-- 控制器

module CP0(
        input clk,
        input rst,
        input teq_exc,
        input mtc0,            //CPU instruction is Mtc0
        input [:] pc,
        input [:] addr,        //Specifies CP0 register
        input [:] wdata,    //Data from GP register to replace CP0 register
        input eret,            //instruction is ERET(Exception Return)
        input [:] cause,
        output [:] rdata,    //Data from CP0 register for GP register,
        output [:] exc_addr    //Address for PC at the beginning of an exception
    );

    parameter    SYSCALL     =   'b1000,
                BREAK       =   'b1001,
                TEQ            =   'b1101,
                IE            =    ;
//                status    =    12,
//                cause        =    13,
//                epc        =    14,    

    reg [:] cop0 [:];
    wire [:] status    =    cop0[];
    integer i;

    wire exception    =    status[]&&    ((status[]&&cause==SYSCALL)||
                                     (status[]&&cause==BREAK)    ||
                                     (status[]&&cause==TEQ&&teq_exc));

    always@(posedge clk or posedge rst) begin
        if(rst)begin
            for(i=;i<;i=i+)
                cop0[i]<=;
        end
        else begin
            if(mtc0)
                cop0[addr]    <=    wdata;
            else if(exception)begin
                cop0[]    <=    pc;
                cop0[]    <=    status<<;
                cop0[]    <=    {'b0,cause,2'b0};
            end
            else if(eret) begin
                cop0[]    <=    status>>;
            end
        end
    end
    assign exc_addr    =    eret?cop0[]:'h4;
    assign rdata    =    cop0[addr];

endmodule