VHDL之Aggregate

Definition

A basic operation that combines one or more values into a composite value of a record or array type.

Example 1

variable Data_1 : BIT_VECTOR ( to ) := ('','','','');

Example 2

variable Data_2 : BIT_VECTOR ( to ) := (=>'',=>'',=>'',=>'');

　　bits 0 and 2 are assigned  '0', while bits 1 and 3 are assigned '1'.

Example 3

signal Data_Bus : std_logic_vector ( downto );
... ...
Data_Bus <= ( downto  => '',  downto  => '');

　　Data_Bus will be assigned "0000_0000_1111_1111".

Example 4

type Status_Record is record
    Code　　: Integer;
    Name　　: String( to );
end record;
variable Status_var : Status_Record := (Code => , Name => "MOVE");

　　each element is associated a value (of the same type as the element itself).

Example 5

signal Data_Bus : std_logic_vector ( downto );
... ...
Data_Bus <= ( downto  => '', others => '');

　　bits 14 through 8 receive value '0' and all the others (15 and 7 through 0) will be assigned '1'.

Example 6

signal Data_Bus : std_logic_vector ( downto );
... ...
Data_Bus <= (others => 'Z');

　　aggregate with the others choice representing all the elements can be used.

Example 7

signal Data_Bus : std_logic_vector ( downto );
... ...
Data_Bus <= ( |  downto  => '', others => '');

　　Note the multiple choice specification of the assignment to the bits 15 and 7 through 0. The result of the assignment to Data_Bus will be the same as in examples 3 and 5 ("1000_0000_1111_1111").