SAP computer之RAM

RAM

　　The RAM is a 16 X 8 static TTL RAM. We can program the RAM by means of the address and data switch registers. This allows us to store a program and data in the memory before a computer run.

　　During a computer run, the RAM receive 4-bit addresses from MAR and a read operation is performed. In this way, the instuction or data word stored in the RAM is placed on the W bus for use in some other part of the computer.

 library IEEE;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 entity ROM_16_8 is
 port
 (
     READ     : in     std_logic;                        --! Active low enable ROM signal, (tri-state)
     ADDRESS  : in     std_logic_vector ( downto );    --! -bit ROM address bits from MAR
     DATA_OUT : out    std_logic_vector ( downto )     --! -bit ROM output word to W-bus
 );
 end ROM_16_8 ;

 architecture beh of ROM_16_8 is

 type mem is array ( to ) of std_logic_vector( downto ) ;
 signal rom : mem;

 begin
20     --! This program works as follow:
21     --!
22     --! Load 5 to AC (memory content of 9)
23     --! Output 5 (content of AC)
24     --! Add 7 (memory content of 10) to 5 (AC content)
25     --! Output 12 (content of AC)
26     --! Add 3 (memory content of 11) to 12 (AC content)
27     --! Subtract 4 (memory content of 12) from 15 (AC content)
28     --! Output 11 (content of AC)
     rom <= (
              => "" ,  -- LDA 9h ... Load AC with the content of memory location 9
              => "" ,  -- OUT
              => "" ,  -- ADD Ah ... Add the contents of memory location A to the AC content and replace the AC
              => "" ,  -- OUT
              => "" ,  -- ADD Bh ... Add the contents of memory location B to the AC content and replace the AC
              => "" ,  -- SUB Ch ... Sub the contents of memory location C from the AC content and replace the AC
              => "" ,  -- OUT
              => "" ,  -- HLT
              => "" ,
              => "" ,   --5
              => "" ,  --7
              => "" ,  --3
              => "" ,  --4
              => "" ,
              => "" ,
              => "" );

     process (READ,ADDRESS)
     begin
         if READ = '' then
             DATA_OUT <= rom(to_integer(unsigned(ADDRESS))) ;
          else
              DATA_OUT <= (DATA_OUT'range => 'Z');
         end if;
    end process ;

 end beh;