PCI Express（二） - Topology

原文出处：http://www.fpga4fun.com/PCI-Express2.html

Point-to-point architecture

At 2.5Gbps, the PCI Express Gen1 line speed is a whopping 75 times faster than the 33MHz legacy PCI speed.
How is that possible? only because PCI express is a point-to-point bus.

在2.5Gbps的速度下，第一代PCI-E是33MHz PCI速度的75倍。这是由于PCI-E使用了点对点总线。

Remember how PCI is a shared bus?

With PCI, ample time has to be specified to let the signals settle during each clock cycle. That's because each line of the PCI bus is shared along the PCI connectors and boards on the same bus. With PCI Express, each signal is point-to-point, which means there is no more settling time and the line speeds can be much higher.

So for example, if a motherboard has two 1-lane connectors and one 16-lane connector, that requires 6+6+34=46 pins on the bridge just for the REFCLKs, PERs and PETs (since no sharing is allowed).

Clock recovery

（这里简单介绍了一下时钟恢复技术，再简单一点：传统的时钟与数据同时传输的并行传输方式无法达到1Gb/s以上带宽，所以引入了时钟数据恢复系统(CDR)，它将数据以8b/10b方式编码并串行发送数据，这种编码方式可以在数据线上传送相等数目的0和1，从而减少码间干扰，并提供足够多的数据边沿，以便接收器在收到的数据流上锁定相位。CDR接收器在RX差分位流上锁定相位，然后接收器按照恢复的时钟进行数据位对齐，接着用接收器的参考时钟进行字对齐。最后，将数据进行8b/10b解码，供系统使用。那么所谓的时钟恢复就是：根据参考时钟，从数据信号把时钟信号提取出来）

At speeds starting at 2.5GHz, the point-to-point architecture is still a challenge to get working because the duration of each bit is so short that timing jitter (the time uncertainty surrounding the arrival of each bit) becomes a problem. And even if each signal pair had an associated clock pair transmitted along with it, the clock pair would also be subject to timing jitter. So instead a new technique called "clock recovery" is used.

Clock recovery is simple. Basically, for each signal pair, the pair receiver looks at the signal transitions (a bit 0 followed by a bit 1, or vice-versa), from which it can infer the position of surrounding bits. One problem is that if many successive bits are transmitted with the same value (like lots of 0's), no signal transition is seen. So extra bits are transmitted to ensure that signals transitions are not too far apart (which "re-synchronizes" the clock recovery mechanism).

The extra bits are sent using a scheme called 8b/10b encoding, so that for each 8 bit of useful data, 10 bits are actually transmitted (a 20% overhead) in a specific way that guarantees enough signal transitions. But that also means that at 2.5GHz, we only get 250MBps of useful bandwidth per pair (instead of the 312MBps we would get without the encoding overhead).

Differential pairs

（简介了差分传输的优缺点）

Now remember the fact that the signals are sent on differential pairs? That has many advantages:

• It is more immune to external interferences.
• It is able to work at low voltage (=lower power consumption).
• ... and last but not least: This helps the clock recovery to get precise signal transitions.

Differential pairs have one obvious disadvantage: it takes twice as many wires to transmit a signal.

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