FMC与FPGA双口ram通讯

硬件环境：ARM+FPGA通过FMC互联，STM32F767和 EP4CE15F23I7

FMC设置,STM的系统时钟HCLK为216MHz

 /* FMC initialization function */
 void MX_FMC_Init(void)
 {
   FMC_NORSRAM_TimingTypeDef Timing;

   /** Perform the NOR1 memory initialization sequence
   */
   hnor1.Instance = FMC_NORSRAM_DEVICE;
   hnor1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
   /* hnor1.Init */
   hnor1.Init.NSBank = FMC_NORSRAM_BANK1;
   hnor1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
   hnor1.Init.MemoryType = FMC_MEMORY_TYPE_NOR;
   hnor1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
   hnor1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
   hnor1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
   hnor1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
   hnor1.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
   hnor1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
   hnor1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
   hnor1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
   hnor1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
   hnor1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
   hnor1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
   hnor1.Init.PageSize = FMC_PAGE_SIZE_NONE;
   /* Timing */
   Timing.AddressSetupTime = ;
   Timing.AddressHoldTime = ;
   Timing.DataSetupTime = ;
   Timing.BusTurnAroundDuration = ;
   Timing.CLKDivision = ;
   Timing.DataLatency = ;
   Timing.AccessMode = FMC_ACCESS_MODE_A;
   /* ExtTiming */

   if (HAL_NOR_Init(&hnor1, &Timing, NULL) != HAL_OK)
   {
     _Error_Handler(__FILE__, __LINE__);
   }
 }

verilog核心代码，其中双口ram的a口与FPGA内部模块相连，b口与ARMFMC端口相连，clk时钟为100MHz

 reg wr_clk1,wr_clk2;.
 wire rd = (cs0 | rdn);
 wire wr = (cs0 | wrn);
 wire clk_b = (!wr_clk2 | !rd);

 ram u1(
     .data_a(data_a),
     .address_a(address_a),
     .wren_a(wren_a),
     .rden_a(rden_a),
     .clock_a(clk_50m),
     .q_a(dataout_a),

     .data_b(db),
     .address_b(ab),
     .wren_b(!wr),
     .rden_b(!rd),
     .clock_b(clk_b),
     .q_b(dataout_b)
 );

 always@(posedge clk_100m or negedge rst_n)
     if(!rst_n)
         begin
             wr_clk1 <= 'd1;
             wr_clk2 <= 'd1;
         end
     else
         {wr_clk2,wr_clk1} <= {wr_clk1,wr};

 assign db = !rd ? dataout_b : 'hzzzz;

在SignalTap中调试发现有时写入丢失（写入后读出不正常），时序上具体体现为

上图中wr信号丢失，造成部分写入失败，wr由ARM输出，与FPGA时钟异步，这里是时钟匹配问题，导致信号丢失，查看STM32F7XX手册关于FMC时序：

图中可以看到,  rd与ADDSET时间有关，wr与DATAST-1时间有关，结合前面FMC程序中

Timing.DataSetupTime = 4；

那么wr理论时间是3*HCLK = 3/216MHZ  ≈14ns， FPGA时钟周期10ns，理论上wr信号不会丢失。猜想可能是异步信号，同时信号边沿存在斜率（有条件可以用示波器捕捉验证），可能存在信号丢失现象，这里修改FMC时间配置参数。

 /* Timing */
   Timing.AddressSetupTime = ;
   Timing.AddressHoldTime = ;
   Timing.DataSetupTime = ;
   Timing.BusTurnAroundDuration = ;
   Timing.CLKDivision = ;
   Timing.DataLatency = ;
   Timing.AccessMode = FMC_ACCESS_MODE_A;

修改后发现以上问题得到解决，调试时序如下：