vivado对task和function的可综合支持

手册UG901,对vivado可综合的语句支持进行了描述，HDL包括：verilog-2001，system-verilog，VHDL；

verilog-2001扩展了对task和function的支持。

ug901手册中，章节7对支持的语法进行详细描述。

 Filename: functions_1.v
 //
 // An example of a function in Verilog
 //
 // File: functions_1.v
 //
 module functions_1 (A, B, CIN, S, COUT);
   input [:] A, B;
   input CIN;
   output [:] S;
   output COUT;
   wire [:] S0, S1, S2, S3;
      function signed [:] ADD;
       input A, B, CIN;
       reg S, COUT;
       begin
           S    = A ^ B ^ CIN;
           COUT = (A&B) | (A&CIN) | (B&CIN);
           ADD  = {COUT, S};
       end
     endfunction

 assign S0 = ADD (A[], B[], CIN),
        S1 = ADD (A[], B[], S0[]),
        S2 = ADD (A[], B[], S1[]),
        S3 = ADD (A[], B[], S2[]),
        S  = {S3[], S2[], S1[], S0[]},
        COUT = S3[];
 endmodule

 Filename: task_1.v
 // Verilog tasks
 // tasks_1.v
 //
 module tasks_1 (A, B, CIN, S, COUT);
    input [:] A, B;
    input CIN;
    output [:] S;
    output COUT;
    reg [:] S;
    reg COUT;
    reg [:] S0, S1, S2, S3;

   task ADD;
       input A, B, CIN;
       output [:] C;
       reg [:] C;
       reg S, COUT;
         begin
            S    = A ^ B ^ CIN;
            COUT = (A&B) | (A&CIN) | (B&CIN);
            C    = {COUT, S};
         end
   endtask

 always @(A or B or CIN)
    begin
        ADD (A[], B[], CIN, S0);
        ADD (A[], B[], S0[], S1);
        ADD (A[], B[], S1[], S2);
        ADD (A[], B[], S2[], S3);
        S    = {S3[], S2[], S1[], S0[]};
        COUT = S3[];
    end

 endmodule

 Filename: asym_ram_tdp_read_first.v
 // Asymetric RAM - TDP
 // READ_FIRST MODE.
 // asym_ram_tdp_read_first.v

 module asym_ram_tdp_read_first
         (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);

 parameter WIDTHB     = ;
 parameter SIZEB      = ;
 parameter ADDRWIDTHB = ;
 parameter WIDTHA     = ;
 parameter SIZEA      = ;
 parameter ADDRWIDTHA = ;

    input                  clkA;
    input                  clkB;
    input                  weA, weB;
    input                  enaA, enaB;
    input [ADDRWIDTHA-:] addrA;
    input [ADDRWIDTHB-:] addrB;
    input [WIDTHA-:]     diA;
    input [WIDTHB-:]     diB;
    output [WIDTHA-:]     doA;
    output [WIDTHB-:]     doB;

 `define max(a,b) {(a) > (b) ? (a) : (b)}
 `define min(a,b) {(a) < (b) ? (a) : (b)}

 function integer log2;
   input integer value;
   reg [:] shifted;
   integer res;
      begin
         if (value < )
            log2 = value;
         else
            begin
               shifted = value-;
               for (res=; shifted>; res=res+)
                  shifted = shifted>>;
                  log2    = res;
            end
      end
 endfunction

 localparam maxSIZE = `max(SIZEA, SIZEB);
 localparam maxWIDTH = `max(WIDTHA, WIDTHB);
 localparam minWIDTH = `min(WIDTHA, WIDTHB);
 localparam RATIO = maxWIDTH / minWIDTH;
 localparam log2RATIO = log2(RATIO);
 reg [minWIDTH-:] RAM [:maxSIZE-];
 reg [WIDTHA-:] readA;
 reg [WIDTHB-:] readB;

   always @(posedge clkB)
     begin
       if (enaB) begin
         readB <= RAM[addrB] ;
         if (weB)
           RAM[addrB] <= diB;
         end
     end

 always @(posedge clkA)
    begin : portA
         integer i;
         reg [log2RATIO-:] lsbaddr ;
         for (i=; i< RATIO; i= i+ ) begin
            lsbaddr = i;
            if (enaA) begin
                  readA[(i+)*minWIDTH - -: minWIDTH] <= RAM[{addrA, lsbaddr}];
                if (weA)
                  RAM[{addrA, lsbaddr}] <= diA[(i+)*minWIDTH- -: minWIDTH];
            end
         end
    end

 assign doA = readA;
 assign doB = readB;
 endmodule

veriilog对常量、结构和编译指令的支持：

Verilog constant
force	Unsupported
release	Unsupported
forever statements	Unsupported
repeat statements	Supported, but repeat value must be constant
for statements	Supported, but bounds must be static
delay (#)	Ignored
event (@)	Unsupported
wait	Unsupported
named events	Unsupported
parallel blocks	Unsupported
specify blocks	Ignored
disable	Supported except in For and Repeat Loop statements
Verilog Design Hierarchies
module definition	Supported
macromodule definition	Unsupported
hierarchical names	Supported
defparam	Supported
array of instances	Supported
Verilog Compiler Directives
`celldefine `endcelldefine	Ignored
`default_nettype	Supported
`define	Supported
`ifdef `else `endif	Supported
`undef, `ifndef, `elsif	Supported
`include	Supported
`resetall	Ignored
`timescale	Ignored
`unconnected_drive `nounconnected_drive	Ignored
`uselib	Unsupported
`file, `line	Supported