In digital logic simulation, a delta cycles are evaluation of expressions, followed by value updates, causing more evaluations, and more value updates, and so on. Each time through the loop is one delta cycle. Different languages have specific definitions of what can happen in a delta cycle, and in most cases, simulation time does not advance in a delta cycle until there is nothing left to do at the current simulation time. Then simulation time is stepped to the next scheduled activity. So there can be one or many delta cycles in a time step. This is the case for SystemVerilog and VHDL.

For synchronous processes, delta delays may be ignored.

If your testbench uses wait statements, you will
discover delta delays. Sim signals will not change
value until a wait is encountered.

Consider writing your testbench in a synchronous
style, using waits only for the sim clock generator.

This not only eliminates the non-stylish "wait for 0 ns",
but it keeps your brain in synchronous mode at all times.

Delta delay affects every assignment to a signal.

A concurrent signal assignment is a process. Take,
for example:

architecture foo of bar is
signal a,b,c: bit;
begin
a <= b and c;
end;

The concurrent assignment "a <= b and c;" is EXACTLY
equivalent to the process

process(b,c) begin
a <= b and c;
end process;

which, in its turn, is exactly equivalent to

process begin
a <= b and c;
wait on b,c;
end process;

In all three cases, the signal assignment suffers a delta delay.

Delta delays allow a discrete-event simulator to be deterministic
without the need for (explicit) mutual exclusion mechanisms.

As Verilog shows, it is possible to define a simulator in which
some signal assignments do NOT suffer delta delays, and yet
retain deterministic behaviour if the user is careful enough. 
The delta delay mechanism is available in Verilog, through 
nonblocking assignment, and is effectively essential when 
writing clock-synchronous descriptions. I say "effectively 
essential" because there are other ways to write clock-
synchronous models, without using nonblocking 
assignment; but they are extremely clumsy and 
error-prone.

what is delta simulation time的更多相关文章

  1. delta simulation time[(delta cycle), (delta delay)]

    "Delta cycles are an HDL concept used to order events that occur in zero physical time."si ...

  2. Verilog Tips and Interview Questions

    Verilog Interiew Quetions Collection :  What is the difference between $display and $monitor and $wr ...

  3. how to forget about delta cycles for RTL design

    A delta cycle is a VHDL construct used to makeVHDL, a concurrent language, executable on asequential ...

  4. Dirac Delta Function

    也称为Degenerate pdf, 退化概率密度函数. 未经考证的解释是: 当正态分布的\(\sigma \to 0\)时, 正态分布就退化为这个分布了. 定义 \[ \delta(x) = \be ...

  5. 数据源增量处理(Delta Proess)三大属性:Recod Mode、Delta Type、Serialization

    声明:原创作品,转载时请注明文章来自SAP师太技术博客( 博/客/园www.cnblogs.com):www.cnblogs.com/jiangzhengjun,并以超链接形式标明文章原始出处,否则将 ...

  6. 对冲的艺术——delta中性交易

    delta中性交易 delta中性交易——外行话 delta中性交易就是构造一个含有期权头寸的组合,使其不受标的股票或指数价格小幅变动的影响.换句话讲,无论标的价格是涨还是跌,组合的市值始终保持不变. ...

  7. Gate level Simulation(门级仿真)

    1 什么是后仿真? 后仿真也成为时序仿真,门级仿真,在芯片布局布线后将时序文件SDF反标到网标文件上,针对带有时序信息的网标仿真称为后仿真. 2 后仿真是用来干嘛的? 检查电路中的timing vio ...

  8. 后勤数据源增量队列Delta Queue(RSA7)中的增量更新区Delta Update、增量重复区Delta Repetition

    声明:原创作品,转载时请注明文章来自SAP师太技术博客:( 博/客/园www.cnblogs.com)www.cnblogs.com/jiangzhengjun,并以超链接形式标明文章原始出处,否则将 ...

  9. fdtd simulation, plotting with gnuplot, writting in perl

    # 9月13日 于成都黄龙溪 1 #!/usr/bin/perl # Author : Leon Email: yangli0534@gmail.com # fdtd simulation , plo ...

随机推荐

  1. 修改UISearchBar的Cancel按钮为中文等本地化问题

    正确方法: 1:创建本地化strings. InfoPlist.strings 2:对InfoPlist.strings添加本地化语言. 即可. 只要添加文件, 系统会根据语言来调整显示文字 常见的搜 ...

  2. 封装一个MongoDB的 asp.net 链接类

    using System; using System.Collections.Generic; using System.Linq; using MongoDB; /// <summary> ...

  3. Apk修改利器:ApkToolkit v2.1

    作 者: Mzucore 时 间: 2013-05-10, 17:18:23 链 接: http://www.unpack.cn/thread-93058-1-1.html 下载地址:http://b ...

  4. Jmeter初步使用二--使用jmeter做一个简单的性能测试

    经过上一次的初步使用,我们懂得了Jmeter的安装与初步使用的方法.现在,我们使用Jmeter做一个简单的性能测试.该次测试,提交的参数不做参数化处理,Jmeter各元件使用将在介绍在下一博文开始介绍 ...

  5. Android UI -- 内容简介

    Android UI(User Interface) 是android学习的必要课程,在接下来的内容我们将主要介绍 Android UI 的基础知识.

  6. 【JS】Intermediate5:Scope

    1.Scope=variable visibility a variable’s scope is the part of your code that can access and modify t ...

  7. SPI介绍

    此文摘自百度百科:http://baike.baidu.com/view/245026.htm SPI概述SPI:高速同步串行口.3-4线接口,收发独立.可同步进行. SPI, 是英语Serial P ...

  8. sqlplus中常用设置参数

    一.各种设置参数解释 转自http://baike.baidu.com/view/1239908.htm Sql*plus是一个最常用的工具,具有很强的功能,主要有: 1. 数据库的维护,如启动,关闭 ...

  9. 【解决】Django下使用sqlite3的相关问题

    最近在玩Django,想用它写一个很小很小的项目,Django自带数据库sqlite3,本来项目也小,我就用它了. 玩意虽小,东西却不是那么好用的. 首先,在项目中建立模型,一个例子是这样的: cla ...

  10. jsp网站与discuz论坛用户同步

    需求分析: 要想实现A(jsp网站)和B(discuz论坛)的同步,这里说的同步指的是 在AB网站任意一方注册之后在另一方都可以直接登录 AB两网站之间的用户登陆状态是同步的,在任意一方登录后,另一方 ...