一段式fsm

//1-paragraph method to decribe FSM
//Describe state transition, state output, state input condition in only 1 always block
//Westor Wang, Dec. 2006
//Verilog Training -- How to write FSM better

module state1 (
               input       nrst,
               input       clk,
               input       i1,
               input       i2,
               output reg  o1,
               output reg  o2,
               output reg  err
               );

reg    [:]   NS; //NextState

parameter [:]      //one hot with zero idle
      IDLE   = 'b000,
      S1     = 'b001,
      S2     = 'b010,
      ERROR  = 'b100;

//1 always block to describe state transition, state output, state input condition
always @ (posedge clk or negedge nrst)
 if (!nrst)
    begin
       NS         <= IDLE;
      {o1,o2,err} <= 'b000;
    end
 else
    begin
       NS         <=  'bx;
      {o1,o2,err} <=  'b000;
      case (NS)
        IDLE:  begin
                 if (~i1)         begin{o1,o2,err}<='b000;NS <= IDLE; end
                 if (i1 && i2)    begin{o1,o2,err}<='b100;NS <= S1;   end
                 if (i1 && ~i2)   begin{o1,o2,err}<='b111;NS <= ERROR;end
               end
        S1:    begin
                 if (~i2)         begin{o1,o2,err}<='b100;NS <= S1;   end
                 if (i2 && i1)    begin{o1,o2,err}<='b010;NS <= S2;   end
                 if (i2 && (~i1)) begin{o1,o2,err}<='b111;NS <= ERROR;end
               end
        S2:    begin
                 if (i2)          begin{o1,o2,err}<='b010;NS <= S2;   end
                 if (~i2 && i1)   begin{o1,o2,err}<='b000;NS <= IDLE; end
                 if (~i2 && (~i1))begin{o1,o2,err}<='b111;NS <= ERROR;end
               end
        ERROR: begin
                 if (i1)          begin{o1,o2,err}<='b111;NS <= ERROR;end
                 if (~i1)         begin{o1,o2,err}<='b000;NS <= IDLE; end
               end
      endcase
   end

endmodule