Verilog学习笔记简单功能实现（五）...............序列检测设计

这里采用夏宇闻教授第十五章的序列检测为例来学习;

从以上的状态转换图可以写出状态机的程序：

 module seqdet(x,out,clk,rst);
   input x,clk,rst;
   output out;
   reg [:]state;
   wire out;
   parameter IDLE='b0,
             A='d1,
             B='d2,
             C='d3,
             D='d4,
             E='d5,
             F='d6,
             G='d7;
   assign out=(state==D&&x==)?:;
   always @(posedge clk or negedge rst)
   begin
   if(!rst)
     state=IDLE;
     else
     case(state)
       IDLE:if(x==) state<=A;
            else state<=IDLE;
       A:if(x==) state<=B;
         else state<=A;
       B:if(x==) state<=C;
         else state<=F;
       C:if(x==) state<=D;
         else state<=G;
       D:if(x==) state<=E;
         else state<=A;
       E:if(x==) state<=C;
         else state<=A;
       F:if(x==) state<=B;
         else state<=A;
       G:if(x==) state<=F;
         else state<=G;
       default: state<=IDLE;
     endcase 

   end
 endmodule

以下是测试模块：

 `timescale 1ns/1ns
 `define halfperiod 

 module testseqdet;
   reg clk,rst;
   reg [:]data;
   wire out,x;
   assign x=data[];
   initial begin
   clk=;
   rst=;
   # rst=;
   # rst=;
   data='b1100_1001_0000_1001_0100;
   end
   always #(`halfperiod) clk=~clk;
   always @(posedge clk)
   begin
   # data={data[:],data[]};
   end
   seqdet m(.x(x),.out(out),.clk(clk),.rst(rst));
 endmodule

其实这里也可以采用六个状态来实现功能：

 1 module seqdet(x,out,clk,rst,state);
 2   input x,clk,rst;
 3   output out;
 4   output [2:0]state;
 5   reg [2:0]state;
 6   wire out;
 7   parameter IDLE=3'd0,
 8             A=3'd1,
 9             B=3'd2,
10             C=3'd3,
11             D=3'd4,
12             E=3'd5;
13   assign out=(state==D&&x==0)?1:0;
14   always @(posedge clk)
15   begin
16   if(!rst)  state<=IDLE;
17   else
18     case(state)
19       IDLE:if(x==1) state<=A;
20            else state<=IDLE;
21       A:if(x==0) state<=B;
22         else state<=A;
23       B:if(x==0) state<=C;
24         else state<=A;
25       C:if(x==1) state<=D;
26         else state<=IDLE;
27       D:if(x==0) state<=E;
28         else state<=A;
29       E:if(x==0) state<=C;
30         else state<=A;
31       default: state<=IDLE;
32     endcase
33   end
34 endmodule

以下是测试模块：

 `timescale 1ns/1ns
 module test_seqdet;
   reg clk,rst;
   reg [:]data;
   wire [:]state;
   wire x,out;
   assign x=data[];
   initial
   begin
   clk=;
   rst=;
   #  rst=;
   # rst=;
   data='b1100_1001_0000_1001_0100;
   end

   always # clk=~clk;
   always @(posedge clk)
   begin
   data={data[:],data[]};
   end
   seqdet m(.x(x),.clk(clk),.rst(rst),.out(out),.state(state));
 endmodule

 

 

也可以用移位寄存器来实现：

 module seqdet
 (
    input wire x,
    input wire clk,
    input wire rst,
    output wire z,
    output reg [:] q
 ); 

 wire [:] q_next; 

 assign q_next ={q[:],x};
 assign z = (q_next== 'b10010) ? 1'b1:'b0; 

 always @ (posedge clk,negedge rst)
    if(!rst)
       q <= 'd0;
    else
       q <= q_next; 

 endmodule

寄存器的实现参照http://www.cnblogs.com/qiweiwang/archive/2011/04/18/2019952.html ，在这里感谢齐威王！